TA0102A.PDF

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TECHNICAL INFORMATION
Stereo 150W (4
Ω
) Class-T Digital Audio Amplifier Driver using
Digital Power Processing (DPP
TM
) Technology
TA0102A
June 2000
General Description
The TA0102A is a 150W continuous average (4Ω), two channel Amplifier Driver Module
TM
which uses Tripath’s proprietary Digital Power Processing (DPP ) technology.
Class-T
amplifiers offer both the audio fidelity of Class-AB and the power efficiency of Class-D
amplifiers.
Applications
Ø
Ø
Ø
Ø
Ø
Audio/Video
Amplifiers/Receivers
Pro-audio Amplifiers
Automobile Power Amplifiers
Subwoofer Amplifiers
Benefits
Ø
Ø
Ø
Reduced system cost with
smaller/less expensive power
supply and heat sink
Signal fidelity equal to high quality
Class-AB amplifiers
High dynamic range compatible
with digital media such as CD and
DVD
Features
Ø
Ø
Ø
Class-T architecture
Proprietary Digital Power
Processing technology
Supports wide range of output
power levels
Ø
“Audiophile” Quality Sound
Ø
0.05% THD+N @ 20W, 8Ω
Ø
0.03% IHF-IM @ 30W, 8Ω
Ø
80W @ 8Ω, 0.1% THD+N,
V
S
= +/-45V
Ø
150W @ 4Ω, 0.1% THD+N,
V
S
= +/-45V
Ø
High Power
Ø
100W @ 8Ω, 1% THD+N,
V
S
= +/-45V
Ø
170W @ 4Ω, 1% THD+N,
V
S
= +/-45V
Ø
High Efficiency
Ø
90% @ 85W @ 8Ω, V
S
=
+/-33.75V
Ø
88% @ 155W @ 4Ω,
V
S
= +/-33.75V
Ø
Dynamic Range = 108 dB
Ø
Requires only N-Channel MOSFET output transistors
Ø
High power supply rejection ratio
Ø
Mute input
Ø
Outputs short circuit protected
Ø
Over- and under-voltage protection
Ø
Bridgeable, single-ended outputs
Ø
38-pin quad package
Ø
Supports 100kHz BW of Super Audio CD and DVD-
Audio (refer to Application Note for specifics)
Typical Performance
THD+N versus Output Power
10
5
20Hz - 22kHz BW
f = 1kHz
BBM = 25nS
Vs = +/-45V
Av = 14.8
ST STP19NB20 MOSFET
2
1
THD+N (%)
0.5
0.2
R
L
= 8
Ω
0.1
0.05
R
L
= 4Ω
0.02
0.01
1
2
5
10
20
50
100
200
Output Power (W)
TA0102A, Rev. 3.1, June 2000
1
TECHNICAL INFORMATION
Absolute Maximum Ratings
SYMBOL
V
S
V5
VN12
T
STORE
T
A
Positive 5V Bias Supply
Supply Voltage: Nominal +12V referenced to V
SNEG
Storage Temperature Range
Operating Free-air Temperature Range
PARAMETER
Supply Voltage (V
SPOS
& V
SNEG
)
VALUE
+/-70
6
18
-40 to 150
-20 to +80
UNITS
V
V
V
°C
°C
Notes: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Damage will occur to the device if VN12 is not supplied or falls below the recommended
operating voltage when V
S
is within its recommended operating range.
Operating Conditions
SYMBOL
V
S
V5
VN12
PARAMETER
Supply Voltage (V
SPOS
& V
SNEG
)
Positive 5V Bias Supply
Supply Voltage: Nominal +12V referenced to V
SNEG
MIN.
+/-28
4.5
10.8
5
12
TYP.
MAX.
+/-49
5.5
13.2
UNITS
V
V
V
Note: Operating Conditions indicate conditions for which the device is functional. See Electrical Characteristics
for guaranteed specific performance limits.
Electrical Characteristics
Unless otherwise specified, T
A
= 25°C. See Notes 1 & 2 for Operating Conditions and Test/Application
Circuit Setup.
SYMBOL
I
q
Quiescent Current
(no load, BBM0=BBM1=0)
PARAMETER
+33.75V
-33.75V
+5V
VN12
MIN.
TYP.
25
30
45
110
5.1
5.2
42
46
+/-28
+/-49
3.5
1
0.315
4
18
0.475
3.5
1
0.63
0.70
77
500
0.77
2
5
25
2
MAX.
75
50
65
160
UNITS
mA
mA
mA
mA
A
A
mA
mA
V
V
V
V
mA
mA
mA
mA
V
V
V
V/V
mV
I
S
I5
IVN12
V
U
V
O
V
IH
- MUTE
V
IL
- MUTE
I
DD
MUTE
Source Current @ P
OUT
= 150W, 4
Ω
+33.75V
-33.75V
Source Current for 5V Bias Supply @ P
OUT
= 150W, R
L
= 4
Ω
Source Current for VN12 Supply @ P
OUT
= 150W, R
L
= 4
Ω
Under Voltage (V
SPOS
& V
SNEG
)
Over Voltage (V
SPOS
& V
SNEG
)
High-level Input Voltage (MUTE)
Low-level Input Voltage (MUTE)
+33.75V
-33.75V
+5V
VN12
High-level Output Voltage (HMUTE & OVERLOADB)
Low-level Output Voltage (HMUTE & OVERLOADB)
Over Current Sense Voltage Threshold
Gain Ratio V
O
/V
I
, R
IN
= 0
Ω
Offset Voltage, no load, MUTE = Logic low (before nulling)
Mute Supply Current
(no load, 145nS delay)
V
OH
V
OL
V
TOC
A
V
Voffset
Minimum and maximum limits are guaranteed but may not be 100% tested.
2
TA0102A, Rev. 3.1, June 2000
TECHNICAL INFORMATION
Performance Characteristics – Single Ended, Vs = +45V
Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. T
A
= 25°C.
See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL
P
OUT
PARAMETER
Output Power
(Continuous Average/Channel)
CONDITIONS
THD+N = 0.1%
R
L
= 8Ω
R
L
= 4Ω
THD+N = 1%
R
L
= 8Ω
R
L
= 4Ω
P
O
= 20W/Channel, R
L
= 8Ω
19kHz, 20kHz, 1:1 (IHF), R
L
= 4Ω
P
OUT
= 30W/Channel
A-Weighted, P
OUT
= 88W/Ch, R
L
= 8Ω
0dBr = 30W, R
L
= 8Ω
f = 120Hz, Vripple = 100 mV
P
OUT
= 230W/Channel, R
L
= 4Ω
A-Weighted, no signal, input shorted,
DC offset nulled to zero
MIN.
TYP.
80
130
100
170
0.05
0.05
98.5
85
67
82
300
MAX.
UNITS
W
W
W
W
%
%
dB
dB
dB
%
µV
THD + N
IHF-IM
SNR
CS
PSRR
η
e
NOUT
Total Harmonic Distortion Plus
Noise
IHF Intermodulation Distortion
Signal-to-Noise Ratio
Channel Separation
Power Supply Rejection Ratio
Power Efficiency
Output Noise Voltage
Performance Characteristics – Single Ended, Vs = +33.75V
Unless otherwise specified, f = 1kHz, Measurement Bandwidth = 22kHz. T
A
= 25°C.
See Notes 1 & 2 for Operating Conditions and Test/Application Circuit Setup.
SYMBOL
P
OUT
PARAMETER
Output Power
(Continuous Average/Channel)
CONDITIONS
R
L
= 8Ω
R
L
= 4Ω
THD+N = 1%
R
L
= 8Ω
R
L
= 4Ω
P
O
= 20W/Channel, R
L
= 8Ω
19kHz, 20kHz, 1:1 (IHF), R
L
= 4Ω
P
OUT
= 30W/Channel
A-Weighted, P
OUT
= 47W/Ch, R
L
= 8Ω
0dBr = 20W, R
L
= 8Ω
f = 120Hz, Vripple = 100 mV
P
OUT
= 85W/Channel, R
L
= 8Ω
A-Weighted, no signal, input shorted,
DC offset nulled to zero
THD+N = 0.1%
MIN.
TYP.
47
77
65
110
0.05
0.03
100
85
67
90
195
MAX.
UNITS
W
W
W
W
%
%
dB
dB
dB
%
µV
THD + N
IHF-IM
SNR
CS
PSRR
η
e
NOUT
Total Harmonic Distortion Plus
Noise
IHF Intermodulation Distortion
Signal-to-Noise Ratio
Channel Separation
Power Supply Rejection Ratio
Power Efficiency
Output Noise Voltage
Minimum and maximum limits are guaranteed but may not be 100% tested.
Notes:
1.
2.
V5 = +5V, VN12 = +12V referenced to V
SNEG
Test/Application Circuit Values:
D = MUR120T3 diodes, R
IN
= 22.1KΩ
R
D
= 33Ω
R
S
= 0.025Ω
R
G
= 30Ω
R
OCR1
= R
OCR2
= 0Ω, L
F
= 18uH (Amidon core T200-2)
C
F
= 0.22uF, C
D
= 0.1uF, C
IN
= 1uF, C
BY
= 0.1uF
Power Output MOSFET, M = ST STP19NB20
BBM0 =BBM1 = 1
TA0102A, Rev. 3.1, June 2000
3
TECHNICAL INFORMATION
Pin Description
Pin
1
2
3
4
5, 6
7, 8
9, 12
10, 11
13, 14
15, 16
17, 30
18, 29
19
20, 27
21, 26
22, 25
23
24
28
31, 32
33, 34
35
36, 37, 38
Function
AGND
OVERLOADB
V5
MUTE
IN2, IN1
BBM0, BBM1
GNDKELVIN1,
GNDKELVIN2
OCR2, OCR1
OCS1L+, OCS1L-
OCS1H-, OCS1H+
LO1COM, LO2COM
FDBKN1;FDBKN2
VN12
LO1, LO2
HO1COM, HO2COM
HO1, HO2
V
SPOS
V
SNEG
PGND
OCS2L-, OCS2L+
OCS2H-, OCS2H+
HMUTE
NC
Description
Analog Ground
Logic output. When low, indicates that the level of the input signal has
overloaded the amplifier.
Positive 5 Volts
Logic input. When high, both amplifiers are muted. When low
(grounded), both amplifiers are fully operational.
Single-ended input (Channel 1 & 2)
Break-before-make timing control
Kelvin connection to speaker ground (Channel 1 & 2)
Over-current threshold adjustment (Channel 1 & 2)
Over Current Sense resistor, Channel 1 low-side
Over Current Sense resistor, Channel 1 high-side
Kelvin connection to source of low-side transistor (Channel 1 & 2)
Feedback (Channel 1 & 2)
Voltage: +12 V from V
SNEG
. Refer to Application Information section.
Low side gate drive output (Channel 1 & 2)
Kelvin connection to source of high-side transistor (Channel 1 & 2)
High side gate drive output (Channel 1 & 2)
Positive supply voltage
Negative supply voltage
Power Ground
Over Current Sense resistor, Channel 2 low-side
Over Current Sense resistor, Channel 2 high-side
Logic output. When high, indicates that the output stages of both
amplifiers are shut off and muted.
Not Connected - Must Be Left Floating
Top View
38
37
36
35
34
33
32
31
30
29
28
38 Pin Quad Module Pin Out
OCS2H+
1
AGND
LO2COM
FDBKN2
OCS2L+
OCS2H-
OCS2L-
HMUTE
PGND
NC
NC
NC
LO2
27
2
OVERLOADB
HO2COM
26
3
V5
HO2
25
4
MUTE
V
SNEG
V
SPOS
24
5
IN2
23
6
IN1
HO1
22
21
7
BBM0
GND KELVIN1
GND KELVIN2
H01COM
8
BBM1
LO1COM
LO1
FDBKN1
VN12
20
9
10
11
12
13
14
15
16
OCS1H+
OCS1L+
OCR2
OCR1
OCS1H-
OCS1L-
17
18
19
Figure 1
4
TA0102A, Rev. 3.1, June 2000
TECHNICAL INFORMATION
Test/Application Circuit
TA0102A
18
16
FDBKN1
OCS1H+
R
S
15 OCS1H-
M
22
C
IN
R
IN
V5
10K
Ω
1M
Ω
0.1 uF
1M
Ω
MUTE
4
IN1
6
HO1
R
G
21 HO1COM
M
20
LO1
R
G
13 OCS1L+
17 LO1COM
14
9
OCR1
R
OCR1
OCR2
R
OCR2
34
BBM0
BBM1
7
R
S
8
33 OCS2H-
M
25
C
IN
IN2
R
IN
V5
10K
Ω
1M
Ω
0.1 uF
1M
Ω
NC
NC
NC
V5
0.1 uF
36
37
23
38
3
AGnd
1
PGnd
28
24
19
V
SPOS
V
SNEG
VN12
32
5
HO2
R
G
26 HO2COM
M
27
LO2
R
G
OCS2L+
R
S
V
SNEG
.1uF
100uF
.1uF
100uF
.1uF
100uF
V
SPOS
D
C
BY
Processing
&
Modulation
L
F
D
C
BY
C
F
R
D
C
D
R
L
R
S
V
SNEG
.1uF
100uF
OCS1L-
GNDKELVIN1
OVERLOADB
HMUTE
FDBKN2
OCS2H+
11
10
2
35
29
V
SPOS
D
C
BY
Processing
&
Modulation
L
F
D
C
BY
C
F
R
D
C
D
R
L
30 LO2COM
31
12
OCS2L-
GNDKELVIN2
NC - Not Connected (Must Be Left Floating)
Note - Heavy Lines Indicate High-Current Paths
Figure 2
TA0102A, Rev. 3.1, June 2000
5

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