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APPLICATION NOTE
0
CoolRunner™ XPLA3 CPLD
0
14*
DS012 (v1.0) January 20, 2000
Advance Product Specification
Features
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Fast Zero Power (FZP™) design technique provides
ultra-low power and very high speed
Innovative XPLA3 architecture combines high speed
with extreme flexibility
Based on industry's first TotalCMOS™ PLD - both
CMOS design and process technologies
Advanced 0.35µ five metal layer E
2
CMOS process
- 1,000 erase/program cycles guaranteed
- 20 years data retention guaranteed
3V, In-System Programmable (ISP) using JTAG IEEE
1149.1 interface
- Full Boundary Scan Test (IEEE 1149.1)
Ultra-low static power of less than 100=µA
Simple deterministic timing model
Support for complex asynchronous clocking
- 16 product term clocks and four local control term
clocks per logic block
- Four global clocks and one universal control term
clock per device
Excellent pin retention during design changes
5V tolerant I/O pins
Input register set up time of 2.0 ns
Logic expandable to 48 product terms
High-speed pin-to-pin delays of 5.0 ns
Slew rate control per macrocell
100% routable
Security bit prevents unauthorized access
Supports hot-plugging capability
Design entry/verification using Xilinx or industry
standard CAE tools
Innovative Control Term structure provides:
- Asynchronous macrocell clocking
- Asynchronous macrocell register preset/reset
- Clock output enable control per macrocell
Four output enable controls per logic block
Foldback NAND for synthesis optimization
Global 3-state which facilitates "bed of nails" testing
Available in Chip-scale BGA, and QFP packages
Commercial and extended voltage industrial grades
Pin compatible with existing CoolRunner low-power
family devices
Family Overview
The CoolRunner XPLA3 (eXtended Programmable Logic
Array) family of CPLDs is targeted for low power systems
that include portable, handheld, and power sensitive appli-
cations. Each member of the XPLA3 family includes Fast
Zero Power (FZP) design technology that combines low
power and high speed. With this design technique, the
XPLA3 family offers true pin-to-pin speeds of 5.0 ns, while
simultaneously delivering power that is less than 100
µA
at
standby without the need for "turbo bits" or other power
down schemes. By replacing conventional sense amplifier
methods for implementing product terms (a technique that
has been used in PLDs since the bipolar era) with a cas-
caded chain of pure CMOS gates, the dynamic power is
also substantially lower than any competing CPLD. Cool-
Runner devices are the only TotalCMOS PLDs, as they use
both a CMOS process technology and the patented full
CMOS FZP design technique.
To the original XPLA architecture, XPLA3 adds a direct
input register path, multiple clocks (both dedicated and
product term generated), and both reset and preset for
each macrocell, with a full PLA structure. These enhance-
ments deliver high speed coupled with very flexible logic
allocation which results in the ability to make design
changes without changing pinout. The XPLA3 logic block
includes a pool of 48 product terms that can be allocated to
any macrocell in the logic block. Logic that is common to
multiple macrocells can be placed on a single PLA product
term and shared, effectively increasing design density.
XPLA3 CPLDs are supported by WebPack from Xilinx and
industry standard CAE tools (Cadence/OrCAD, Exemplar
Logic, Mentor, Synopsys, Viewlogic, andd Synplicity), using
text (ABEL, VHDL, Verilog) and schematic capture design
entry. Design verification uses industry standard simulators
for functional and timing simulation. Development is sup-
ported on personal computer, Sparc, and HP platforms.
Device fitting uses Xilinx developed tools including Webfit-
ter.
The XPLA3 family features also include industry-standard,
IEEE 1149.1, JTAG interface through which In-System Pro-
gramming (ISP) and reprogramming of the device can
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DS012 (v1.0) January 20, 2000
www.xilinx.com
1-800-255-7778
1
R
CoolRunner™ XPLA3 CPLD
occur. The XPLA3 CPLD is electrically reprogrammable
using industry standard device programmers from vendors
such as Data I/O, BP Microsystems, and SMS.
clock terms, and logic cells. There are 36 pairs of true and
complement inputs from the ZIA that feed the 48 product
terms in the array. Within the 48 p-terms there are eight
local control terms (LCT[0:7]) available as control inputs to
each macrocell for use as asynchronous clocks, resets,
presets and output enables. The other p-terms serve as
additional single inputs into each macrocell.
There are eight foldback NAND p-terms that are available
for ease of fitting and pin locking. Sixteen product terms are
coupled with the associated programmable OR gate into
the VFM (Variable Function Multiplexer). The VFM
increases logic optimization by implementing any two input
logic funtion before entering the macrocell (see
Figure 3).
Each macrocell can support combinatorial or registered
inputs, preset and reset on a per macrocell basis and con-
figurable D, T registers, or latch funtion. If a macrocell
needs more product terms, it simply gets the additional
product terms from the PLA array.
XPLA3 Architecture
Figure 1
shows a high-level block diagram of a 128 macro-
cell device implementing the XPLA3 architecture. The
XPLA3 architecture consists of logic blocks that are inter-
connected by a Zero-power Interconnect Array (ZIA). The
ZIA is a virtual crosspoint switch. Each logic block has 36
inputs from the ZIA and 16 macrocells.
From this point of view, this architecture looks like many
other CPLD architectures. What makes the XPLA3 family
unique is logic allocation inside each logic block and the
design technique used to implement these logic blocks.
Logic Block Architecture
Figure 2
illustrates the logic block architecture. Each logic
block contains a PLA array that generates control terms,
I/O
MC0
MC1
MC15
LOGIC
BLOCK
36
36
LOGIC
BLOCK
MC0
MC1
MC15
I/O
16
16
16
16
I/O
MC0
MC1
MC15
LOGIC
BLOCK
36
36
LOGIC
BLOCK
MC0
MC1
MC15
I/O
16
16
16
ZIA
16
I/O
MC0
MC1
MC15
LOGIC
BLOCK
36
36
LOGIC
BLOCK
MC0
MC1
MC15
I/O
16
16
16
16
I/O
MC0
MC1
MC15
LOGIC
BLOCK
36
36
LOGIC
BLOCK
MC0
MC1
MC15
I/O
16
16
16
16
ds012_01_121399
Figure 1: Xilinx XPLA3 CPLD Architecture
DS012 (v1.0) January 20, 2000
www.xilinx.com
1-800-255-7778
2
R
CoolRunner™ XPLA3 CPLD
8
Foldback NAND
(P
T
[8:15])
To Universal Control Term (UCT) Mux
To Local Control Term (LCT0)
1
ZIA
Product
Term
Array
36 x 48
(P
T
0)
1
To Local Control Term (LCT7)
(P
T
7)
36
(P
T
[32:47])
P-term Clocks
ZIA
1
(P
T
16)
48
VFM
2
D
Q
I/O0
Macrocell 0
(P
T
[0:47])
ZIA
1
48
2
(PT31)
VFM
D
Q
I/O15
Macrocell 15
(P
T
[0:47])
ds012_02_1230 99
Figure 2:
Xilinx XPLA3 Logic Block Architecture
3
www.xilinx.com
1-800-255-7778
DS012 (v1.0) January 20, 2000
R
CoolRunner™ XPLA3 CPLD
From P-term
To Combinatorial Path
and Register Input
From PLA OR Term
ds012_03_121699
Figure 3: Variable Function Multiplexer
FoldBack NANDs
XPLA3 utilizes FoldBack NANDs to increase the effective
product term width of a programmable logic device. These
structures effectively provide an inverted product term to be
used as a logic input by all of the local product terms. Refer
to
Figure 4
for an example of this technique. .
P
T
1
P
T
2
To MC
P
T
3
A#B#C
P
T
4
!A & !B & !C
Macrocell Architecture
Figure 5
shows the architecture of the macrocell used in
the CoolRunner XPLA3. Any macrocell can be reset or pre-
set on power-up. Each macrocell register can be config-
ured as a D-, T-, or Latch-type flip-flop, or combinatorial
logic function. Each of these flip-flops can be clocked from
any one of eight sources. There are two global synchro-
nous clocks that are derived from the four external clock
pins. There is one universal clock signal. The clock input
signals CT[4:7] (Local Control Terms) can be individually
configured as either a PRODUCT term or SUM term equa-
tion created from the 36 signals available inside the logic
block. Each macrocell register can be configured to be Pre-
set or Reset upon power-up.
There are two feedback paths to the ZIA: one from the mac-
rocell, and one from the I/O pin. When the I/O pin is used as
an output, the output buffer is enabled, and the macrocell
feedback path can be used to feed back the logic imple-
mented in the macrocell. When an I/O pin is used as an
input, the output buffer will be 3-stated and the input signal
will be fed into the ZIA via the I/O feedback path. The logic
implemented in the buried macrocell can be fed back to the
ZIA via the macrocell feedback path.
If the macrocell is configured as an input, there is a path to
the register to provide a fast input setup time.
ds012_04_123099
Figure 4: Basic FoldBack NAND Structure
As seen in Figure 4, the output signal is determined by the
following equation:
MC logic = PT1 # PT2 # PT3 # (PT4) &(A # B # C)
DS012 (v1.0) January 20, 2000
www.xilinx.com
1-800-255-7778
4
R
CoolRunner™ XPLA3 CPLD
Universal PST
CT [0:5]
To ZIA
PAD
To ZIA
From PT Array
1
48
PLA OR Term
VFM
PST
D/T/L Q
CT4
P-term
CLKEn
RST
To I/O
Global CLK
Global CLK
Universal CLK
P-term CLK
CT [4:7]
Universal RST
CT [0:5]
Note:
Global CLK signals come from pins.
ds012_05_122299
Figure 5: XPLA3 Macrocell Architecture
I/O Cell
The OE (Output Enable) multiplexer has eight possible
modes (Figure
4),
including a programmable weak pull-up
(WPU) eliminating the need for external termination on
unused I/Os.
To Macrocell / ZIA
V
CC
WP
Weak Pull-up
OE = 7
The I/O Cell is 5V tolerant, and has a single-bit slew-rate
control for reducing EMI generation.
Outputs are 3.3V PCI electrical specification compatible
(no internal clamp diode).
From Macrocell
Slew
Control
GND
CT
Universal OE
V
CC
GND (Weak P.U.)
3
4
I/O Pin
OE [2:0]
OE
Decode
0
1
2
3
4
5
6
7
I/O Pin
State
3-State
Function CT0
Function CT1
Function CT2
Function CT6
Universal OE
Enable
Weak P.U.
ds012_06_121699
Figure 6: I/O Cell
5
www.xilinx.com
1-800-255-7778
DS012 (v1.0) January 20, 2000

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