VHDL for Logic Synthesis, 3rd Edition.pdf

(4480 KB) Pobierz
VHDL FOR LOGIC
SYNTHESIS
Third Edition
VHDL for Logic Synthesis,
Third Edition. Andrew Rushton.
© 2011 John Wiley & Sons, Ltd. Published 2011 by John Wiley & Sons, Ltd. ISBN: 978-0-470-68847-2
www.allitebooks.com
VHDL FOR LOGIC
SYNTHESIS
Third Edition
Andrew Rushton
www.allitebooks.com
This edition first published 2011
Ó
2011 John Wiley & Sons, Ltd.
Registered office
John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, United Kingdom
For details of our global editorial offices, for customer services and for information about how to apply for permission to
reuse the copyright material in this book please see our website at www.wiley.com.
The right of the author to be identified as the author of this work has been asserted in accordance with the Copyright,
Designs and Patents Act 1988.
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any
form or by any means, electronic, mechanical, photocopying, recording or otherwise, except as permitted by the UK
Copyright, Designs and Patents Act 1988, without the prior permission of the publisher.
Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available
in electronic books.
Designations used by companies to distinguish their products are often claimed as trademarks. All brand names and
product names used in this book are trade names, service marks, trademarks or registered trademarks of their respective
owners. The publisher is not associated with any product or vendor mentioned in this book. This publication is designed
to provide accurate and authoritative information in regard to the subject matter covered. It is sold on the understanding
that the publisher is not engaged in rendering professional services. If professional advice or other expert assistance is
required, the services of a competent professional should be sought.
Library of Congress Cataloging-in-Publication Data
Rushton, Andrew.
VHDL for logic synthesis / Andrew Rushton. – 3rd ed.
p. cm.
Includes index.
Summary: ‘‘Macrocycles: Construction, Chemistry and Nanotechnology Applications is an essential introduction this
important class of molecules and describes how to synthesise them, their chemistry, how they can be used as
nanotechnology building blocks, and their applications’’– Provided by publisher.
ISBN 978-0-470-68847-2 (hardback)
1. VHDL (Computer hardware description language) 2. Logic design–Data processing. 3. Computer-aided design.
I. Title.
TK7885.7.R87 2011
621.39
0
5–dc22
2010045678
A catalogue record for this book is available from the British Library.
Print ISBN: 9780470688472
E-PDF ISBN: 9780470977927
O-book ISBN: 9781119995852
E-Pub ISBN: 9780470977972
Set in 10/12pt Times by Thomson Digfital, Noida, India.
Printed in [Country] by [Printer]
www.allitebooks.com
Contents
Preface
List of Figures
List of Tables
1
Introduction
1.1 The VHDL Design Cycle
1.2 The Origins of VHDL
1.3 The Standardisation Process
1.4 Unification of VHDL Standards
1.5 Portability
Register-Transfer Level Design
2.1 The RTL Design Stages
2.2 Example Circuit
2.3 Identify the Data Operations
2.4 Determine the Data Precision
2.5 Choose Resources to Provide
2.6 Allocate Operations to Resources
2.7 Design the Controller
2.8 Design the Reset Mechanism
2.9 VHDL Description of the RTL Design
2.10 Synthesis Results
Combinational Logic
3.1 Design Units
3.2 Entities and Architectures
3.3 Simulation Model
3.4 Synthesis Templates
3.5 Signals and Ports
3.6 Initial Values
3.7 Simple Signal Assignments
3.8 Conditional Signal Assignments
xi
xv
xvii
1
1
2
3
4
4
7
8
8
10
12
12
13
14
15
15
16
19
19
20
22
25
27
29
30
31
2
3
www.allitebooks.com
vi
Contents
3.9 Selected Signal Assignment
3.10 Worked Example
4
Basic Types
4.1 Synthesisable Types
4.2 Standard Types
4.3 Standard Operators
4.4 Type Bit
4.5 Type Boolean
4.6 Integer Types
4.7 Enumeration Types
4.8 Multi-Valued Logic Types
4.9 Records
4.10 Arrays
4.11 Aggregates, Strings and Bit-Strings
4.12 Attributes
4.13 More on Selected Signal Assignments
Operators
5.1 The Standard Operators
5.2 Operator Precedence
5.3 Boolean Operators
5.4 Comparison Operators
5.5 Shifting Operators
5.6 Arithmetic Operators
5.7 Concatenation Operator
Synthesis Types
6.1 Synthesis Type System
6.2 Making the Packages Visible
6.3 Logic Types – Std_Logic_1164
6.4 Numeric Types – Numeric_Std
6.5 Fixed-Point Types – Fixed_Pkg
6.6 Floating-Point Types – Float_Pkg
6.7 Type Conversions
6.8 Constant Values
6.9 Mixing Types in Expressions
6.10 Top-Level Interface
Std_Logic_Arith
7.1 The Std_Logic_Arith Package
7.2 Contents of Std_Logic_Arith
7.3 Type Conversions
7.4 Constant Values
7.5 Mixing Types in Expressions
33
34
37
37
37
38
39
39
41
46
47
48
49
53
56
60
63
63
64
70
73
76
79
84
85
85
87
90
95
105
119
134
144
146
147
151
151
152
161
162
164
5
6
7
www.allitebooks.com

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin