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ISSUE 50, FALL 2004
XCELL JOURNAL
XILINX, INC.
T H E A U T H O R I
I
T A T I
I
V E J O U R N A L F O R P R O G R A M M A B L E L O G I
I
C U S E R S
THE AUTHOR TAT VE JOURNAL FOR PROGRAMMABLE LOG C USERS
Xcell
journal
Issue 50
Fall 2004
MEMORY DESIGN
Streaming Data at 10 Gbps
Control Your QDR Designs
PARTNERSHIP
20 Years of Partnership
Author! Author!
Programmable World 2004
SOFTWARE
Algorithmic C Synthesis
The Need for Speed
MANUFACTURING
Lower PCB Mfg. Costs
Optimize PCB Routability
R
COVER STORY
FPGAs on Mars
The New
SPARTAN-3
™
Make It
Your
ASIC
The world’s lowest-cost FPGAs
Spartan-3 Platform FPGAs deliver everything you need at the price you want. Leading the way in 90nm
process technology, the new Spartan-3 devices are driving down costs in a huge range of high-capability,
cost-sensitive applications. With the industry’s widest density range in its class — 50K to 5 Million
gates — the Spartan-3 family gives you unbeatable value and flexibility.
Lots of features … without compromising on price
Check it out. You get 18x18 embedded multipliers for XtremeDSP
™
processing in a low-cost
FPGA. Our unique staggered pad technology delivers a ton of I/Os for total connectivity
solutions. Plus our XCITE technology improves signal integrity, while eliminating hundreds
of resistors to simplify board layout and reduce your bill of materials.
With the lowest cost per I/O and lowest cost per logic cell, Spartan-3 Platform
FPGAs are the perfect fit for any design … and any budget.
MAKE IT YOUR ASIC
The Programmable Logic Company
SM
For more information visit
www.xilinx.com/spartan3
Pb-free devices
available now
©2004 Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Europe +44-870-7350-600; Japan +81-3-5321-7711; Asia Pacific +852-2-424-5200; Xilinx is a registered trademark, Spartan and XtremeDSP are trademarks, and The Programmable Logic Company is a service mark of Xilinx, Inc.
L E T T E R
F R O M
T H E
E D I T O R
Thank You for Making
Xilinx Number One
EDITOR IN CHIEF
Carlis Collins
editor@xilinx.com
408-879-4519
Forrest Couch
forrest.couch@xilinx.com
408-879-5270
MANAGING EDITOR
ASSISTANT MANAGING EDITOR Charmaine Cooper Hussain
XCELL ONLINE EDITOR
Tom Pyles
tom.pyles@xilinx.com
720-652-3883
Dan Teie
1-800-493-5551
Scott Blair
E
Ever have one of those days where you’re working hard, nose to the grindstone, striving to make sure
your latest project is on time and on target; and then suddenly out of nowhere, you overhear some-
one complimenting your efforts? It’s not a comment that you solicited, but independently you find
out that all of your hard work is recognized as the best among your peers and you’re headed in the
right direction.
CMP Media LLC, the parent company of
EETimes,
just dropped quite a few kudos on the Xilinx
doorstep. Most of you know that every year CMP conducts a PCB and IC electronic design tool
industry survey to sample the engineering community’s view on design tool providers. This year, at the
2004 Design Automation Conference, CMP announced the results of their first FPGA vendor survey.
The ratings are striking. In 21 out of 22 categories measuring everything from best pre-sales support
to brand and tool awareness, from most ethical company to customer loyalty, FPGA designers chose
Xilinx as the top FPGA vendor. We received the highest rankings in best after-sales support, best
documentation, current technology leader, technology leader in three years, clear vision of the
future, best integration with other vendors’ tools, well-managed company, and more.
We were also able to hear the industry concerns. Respondents cited the accuracy and integrity of FPGA
tools as their biggest design issue, followed closely by functional verification, timing closure, and the
ability of those tools to easily handle complex designs. They also said that the majority of their design
time was spent in place and route, synthesis, and HDL simulation, followed by timing analysis and
floorplanning. One-third of the respondents also use formal verification, while almost half regularly
use signal integrity and C language system-level tools.
On behalf of all of the employees at Xilinx, thank you. We hear you loud and clear. Our primary goal
is to put a programmable device in every piece of electronic equipment over the next 10 years. It’s nice
to hear that we’re on the right path to get there.
ADVERTISING SALES
ART DIRECTOR
Xcell
journal
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124-3400
Phone: 408-559-7778
FAX: 408-879-4780
©2004 Xilinx, Inc.
All rights reserved.
The
Xcell Journal
is published quarterly. XILINX, the Xilinx
logo, CoolRunner, RocketChips, Rocket IP, Spartan,
StateBENCH, StateCAD, Virtex, Virtex-II, and XACT are regis-
tered trademarks of Xilinx, Inc. ACE Controller, ACE Flash,
Alliance Series, AllianceCORE, Bencher, ChipScope,
Configuration Logic Cell, CORE Generator, CoreLINX, Dual
Block, EZTag, Fast CLK, Fast CONNECT, Foundation, Gigabit
Speeds…and Beyond!, HardWire, HDL Bencher, IRL, J
Drive, Jbits, LCA, LogiBLOX, Logic Cell, Logic Professor,
MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze,
PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI,
RocketIO, RocketPHY, SelectIO, SelectRAM, SelectRAM+,
Silicon Xpresso, Smartguide, Smart-IP, SmartSearch,
SMARTswitch, System ACE, Testbench In A Minute, TrueMap,
UIM, VectorMaze, VersaBlock, VersaRing, Virtex-4, Virtex-II
Pro, Virtex-II Pro X, Virtex-II EasyPath, Wave Table,
WebFITTER, WebPACK, WebPOWERED, XABLE, XAPP, X-
BLOX+, XC designated products, XChecker, XDM, XEPLD,
Xilinx Foundation Series, Xilinx XDTV, Xinfo, XtremeDSP,
and ZERO+ are trademarks, and The Programmable Logic
Company is a service mark of Xilinx, Inc. Other brand or
product names are registered trademarks or trademarks of
their respective owners.
The articles, information, and other materials included in
this issue are provided solely for the convenience of our
readers. Xilinx makes no warranties, express, implied,
statutory, or otherwise, and accepts no liability with respect
to any such articles, information, or other materials or
their use, and any use thereof is solely at the risk of the
user. Any person or entity using such information in any
way releases and waives any claim it might have against
Xilinx for any loss, damage, or expense caused thereby.
Forrest Couch
Managing Editor
F A L L
2 0 0 4,
I S S U E
5 0
Xcell
journal
View from the Top ................................................................5
FPGAs on Mars.....................................................................8
Streaming Data at 10 Gbps .................................................13
Control Your QDR Designs ....................................................16
Celebrating 20 Years of Partnership.......................................21
Author! Author! .................................................................25
Experience Programmable World 2004..................................30
Managing Partial Dynamic Reconfiguration .............................32
Nucleus RTOS for Xilinx FPGAs..............................................38
Implement an Embedded System with FPGAs .........................43
Algorithmic C Synthesis .......................................................46
Design Tool Performance Lowers Costs...................................52
The Need for Speed ............................................................54
COVER STORY
FPGAs on Mars
Xilinx FPGAs have transitioned from
a flight ASIC prototyping platform
to playing integral roles in the
Mars Exploration Rover Mission.
8
Streaming Data
at 10 Gbps
Using a Virtex-II FPGA to
stream data from DDR-SDRAM
to OC-192 serializers.
13
Celebrating 20 Years
of Partnership
Turning an industry cliché into
a successful business model.
Lower Your PCB Manufacturing Costs.....................................57
Plan FPGA Signal Assignments..............................................60
Next-Generation Data Transport.............................................64
Designing Next-Generation Wireless Systems ..........................68
Meeting Interoperability Standards ........................................70
Xilinx Partner Yellow Pages ..................................................74
Reference Pages.................................................................82
21
Next-Generation Data
Transport over Metro
Area Networks
The Xilinx GFP core enables efficient
transport of LAN/SAN over
SONET-based networks.
64
To receive a free subscription
to the printed
Xcell Journal
,
or to view the Web-based
Xcell Online
,
visit
www.xilinx.com/xcell/
.
View
from the top
Preparing for a Bright Future
The economy is improving and most
analysts predict that the semiconductor
industry will grow for the next two years.
Here’s what I see ahead for Xilinx.
We recently emerged
from a three-year
recession that was one
of the longest and
deepest in our history,
yet things are getting
better. The semicon-
ductor industry typi-
cally moves in a
by Wim Roelandts
two-year cycle, unless
CEO, Xilinx, Inc.
it is influenced by
events such as the 9/11 tragedy. Therefore, after
two years of growth, an overbuilding of capacity
will likely occur, with another market correction
in 2006. This is a normal and predictable cycle;
it’s the way our industry usually works.
These capacity-driven recessions tend to be
shallow and short – the last one was in 1996
and lasted about 18 months. For Xilinx
®
dur-
ing that period, we had a few negative growth
quarters, with an overall 1% growth.
The market recovery is still fragile, driven
primarily by the U.S. and China. And not all of
the industries that we deal with are yet in recov-
ery, which I think is good because it helps us
maintain a steady growth pattern as they begin
to improve later in the year.
Overall, Xilinx is in an extremely good posi-
tion – our business processes, our manufactur-
ing technology, our circuit innovation, and our
software are poised to take full advantage of the
current market conditions.
Fall 2004
Xcell Journal
5

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