schematic.pdf

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1
2
3
4
J1
2
3
1
U1
D1
4
3
AC
V-
Bridge2
GND
GND
R3
680
D4
U2
B16
PC0 (ADC0)
PC1 (ADC1)
PC2 (ADC2)
PC3 (ADC3)
PC4 (ADC4/SDA)
PC5 (ADC5/SCL)
ADC6
ADC7
PC6 (RESET)
VCC
VCC
AVCC
AREF
GND
GND
GND
23
24
25
26
27
28
19
22
29
RST
VCC
6
4
18
20
21
5
3
680
D10
C5
100nF
B4
R12
680
D13
ATmega8-16AI
B2
GND
R15
VCC
VCC
R19
4k7
Key1
VCC
R20
4k7
Key2
R18
10K
P1
MOSI
RST
SCK
MISO
1
3
5
7
9
2
4
6
8
10
VCC
B1
680
D16
R16
680
D17
R17
680
D18
R13
680
D14
R14
680
D15
C
680
D11
680
D12
R6
680
D7
B8
R9
R10
R11
R7
680
D8
R8
680
D9
B
R4
680
D5
R5
680
D6
AC
V+
2
1
C2
47uF
1
IN
OUT
GND
4
3
C1
47uF
VCC
SECONDS
MINUTES
HOURS
A
A
PWR2.5
R1
680
R2
680
D2
D3
L7805ABD2T
GND
GND
B32
B
B4
12
B2
13
B1
14
MOSI
15
MISO
16
SCK
17
7
8
2
Y1
1
Key2
Key1
HOURS
MINUTES
B32
B16
SECONDS
B8
30
31
32
1
2
9
10
11
PB0 (ICP)
PB1 (OC1A)
PB2 (SS/OC1B)
PB3 (MOSI/OC2)
PB4 (MISO)
PB5 (SCK)
PB6 (XTAL1/TOSC1)
PB7 (XTAL2/TOSC2)
PD0 (RXD)
PD1 (TXD)
PD2 (INT0)
PD3 (INT1)
PD4 (XCK/T0)
PD5 (T1)
PD6 (AIN0)
PD7 (AIN1)
32768
C3
15pF
C4
15pF
GND
C
GND
GND
S1
S2
D
GND
SW-DPST
GND
SW-DPST
Title
Binary clock
Size
GND
A4
Date:
File:
18.12.2008
D:\altium\binary_clock\Sheet1.SchDoc
Sheet of
Drawn By:
4
Number
Revision
1.0
D
Header 5X2
1
2
3

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