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LMX2306/LMX2316/LMX2326 PLLatinum Low Power Frequency Synthesizer for RF Personal
Communications
ADVANCE INFORMATION
January 1998
LMX2306/LMX2316/LMX2326
PLLatinum
™
Low Power Frequency Synthesizer for RF
Personal Communications
LMX2306
550 MHz
LMX2316
1.2 GHz
LMX2326
2.8 GHz
General Description
The LMX2306/16/26 are monolithic, integrated frequency
synthesizers with prescalers that are designed to be used to
generate a very stable low noise signal for controlling the lo-
cal oscillator of an RF transceiver. They are fabricated using
National’s ABiC V silicon BiCMOS 0.5µ process.
The LMX2306 contains a 8/9 dual modulus prescaler while
the LMX2316 and the LMX2326 have a 32/33 dual modulus
prescaler. The LMX2306/16/26 employ a digital phase
locked loop technique. When combined with a high quality
reference oscillator and loop filter, the LMX2306/16/26 pro-
vide the feedback tuning voltage for a voltage controlled os-
cillator to generate a low phase noise local oscillator signal.
Serial data is transferred into the LMX2306/16/26 via a three
wire interface (Data, Enable, Clock). Supply voltage can
range from 2.3V to 5.5V. The LMX2306/16/26 feature ultra
low current consumption; LMX2306 - 1.7 mA at 3V,
LMX2316 - 2.5 mA at 3V, and LMX2326 - 4.0 mA at 3V.
The LMX2306/16/26 synthesizers are available in a 16-pin
TSSOP surface mount plastic package.
Features
n
n
n
n
n
2.3V to 5.5V operation
Ultra low current consumption
2.5V V
CC
JEDEC standard compatible
Programmable or logical power down mode:
— I
CC
= 1 µA typical at 3V
Dual modulus prescaler:
— LMX2306
8/9
— LMX2316/26
32/33
Selectable charge pump TRI-STATE
®
mode
Selectable FastLock
™
mode with timeout counter
MICROWIRE
™
Interface
Digital Lock Detect
n
n
n
n
Applications
n
n
n
n
n
Portable wireless communications (PCS/PCN, cordless)
Wireless Local Area Networks (WLANs)
Cable TV tuners (CATV)
Pagers
Other wireless communication systems
Functional Block Diagram
DS100127-1
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
FastLock
™
, PLLatinum
™
and MICROWIRE
™
are trademarks of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100127
www.national.com
Connection Diagram
LMX2306/16/26
DS100127-2
16-Lead (0.173” Wide) Thin Shrink Small Outline Package(TM)
Order Number LMX2306TM, LMX2306TMX, LMX2316TM, LMX2316TMX,
LMX2326TM or LMX2326TMX
See NS Package Number MTC16
Pin Description
16-Pin
1
2
3
4
5
Pin
Name
FL
o
CP
o
GND
GND
f
IN
I
I/O
O
O
Description
FastLock Output. For connection of parallel resistor to the loop filter. (See Section 1.3.4
FASTLOCK MODES description.)
Charge Pump Output. For connection to a loop filter for driving the input of an external VCO.
Charge Pump Ground.
Analog Ground.
RF Prescaler Complementary Input. A bypass capacitor should be placed as close as possible to
this pin and be connected directly to the ground plane. The complementary input can be left
unbypassed, with some degradation in RF sensitivity.
RF Prescaler Input. Small signal input from the VCO.
Analog Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin and be connected directly to the ground plane. V
CC1
must equal V
CC2
.
I
Oscillator Input. This input is a CMOS input with a threshold of approximately V
CC
/2 and an
equivalent 100k input resistance. The oscillator input is driven from a reference oscillator.
Digital Ground.
I
Chip Enable. A LOW on CE powers down the device and will TRI-STATE the charge pump output.
Taking CE HIGH will power up the device depending on the status of the power down bit F2. (See
Section 1.3.1 POWERDOWN OPERATION and Section 1.7.1 DEVICE PROGRAMMING AFTER
FIRST APPLYING V
CC
.)
High Impedance CMOS Clock Input. Data for the various counters is clocked in on the rising edge
into the 21-bit shift register.
Binary Serial Data Input. Data entered MSB first. The last two bits are the control bits. High
impedance CMOS input.
Load Enable CMOS Input. When LE goes HIGH, data stored in the shift registers is loaded into one
of the 3 appropriate latches (control bit dependent).
Multiplexed Output of the RF Programmable or Reference Dividers and Lock Detect. CMOS output.
(See
Table 4.)
Digital Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin and be connected directly to the ground plane. V
CC1
must equal V
CC2
.
Power Supply for Charge Pump. Must be
≥
V
CC
.
6
7
f
IN
V
CC1
I
8
9
10
OSC
IN
GND
CE
11
12
13
14
15
Clock
Data
LE
Fo/LD
V
CC2
I
I
I
O
16
V
P
www.national.com
2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Power Supply Voltage
V
CC1
V
CC2
V
p
Voltage on Any Pin
with GND = 0V (V
I
)
Storage Temperature Range (T
S
)
Lead Temperature (T
L
)
(solder, 4 sec.)
−0.3V to +6.5V
−0.3V to +6.5V
−0.3V to +6.5V
−0.3V to V
CC
+ 0.3V
−65˚C to +150˚C
+260˚C
Recommended Operating
Conditions
Min
Power Supply Voltage
V
CC1
V
CC2
V
p
Operating Temperature (T
A
)
2.3
V
CC1
V
CC
−40
Max
5.5
V
CC1
5.5
+85
Units
V
V
V
˚C
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to
the device may occur. Recommended operating conditions indicate condi-
tions for which the device is intended to be functional, but do not guarantee
specific performance limits. For guaranteed specifications and test condi-
tions, see the Electrical Characteristics. The guaranteed specifications apply
only for the test conditions listed.
Note 2:
This device is a high performance RF integrated circuit with an ESD
rating
<
2 keV and is ESD sensitive. Handling and assembly of this device
should only be done at ESD protected work stations.
Electrical Characteristics
V
CC
= 3.0V, V
p
= 3.0V; −40˚C
<
T
A
<
85˚C except as specified
Symbol
I
CC
Parameter
Power Supply Current
LMX2306
LMX2316
LMX2326
I
CC-PWDN
f
IN
Powerdown Current
RF Input Operating
Frequency
LMX2306
LMX2316
LMX2326
f
osc
fφ
Pf
IN
P
osc
V
IH
V
IL
I
IH
I
IL
I
IH
I
IL
ICP
o-source
ICP
o-sink
ICP
o-source
ICP
o-sink
ICP
o-Tri
ICP
o-sink vs
ICP
o-source
Charge Pump TRI-STATE Current
CP Sink vs Source Mismatch
Maximum Oscillator Frequency
Maximum Phase Detector Frequency
RF Input Sensitivity
Oscillator Sensitivity
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
Oscillator Input Current
Oscillator Input Current
Charge Pump Output Current
V
CC
= 3.0V
V
CC
= 5.0V
OSC
IN
(Note 4)
(Note 4)
V
IH
= V
CC
= 5.5V (Note 4)
V
IL
= 0V, V
CC
= 5.5V
(Note 4)
V
IH
= V
CC
= 5.5V
V
IL
= 0V, V
CC
= 5.5V
V
Do
= V
p
/2, ICP
o
= LOW
(Note 3)
V
Do
= V
p
/2, ICP
o
= LOW
(Note 3)
V
Do
= V
p
/2, ICP
o
= HIGH
(Note 3)
V
CPo
= V
p
/2, ICP
o
= HIGH
(Note 3)
0.5
≤
V
CPo
≤
V
p
− 0.5
−40˚C
<
T
A
<
85˚C
V
CPo
= V
p
/2
T
A
= 25˚C
−1.0
−1.0
−15
−10
−5
0.8 x V
CC
0.2 x
V
CC
1.0
1.0
100
−100
−250
250
−1.0
1.0
−1.0
5
1.0
Conditions
Min
V
CC
= 2.3V to 5.5 V
V
CC
= 2.3V to 5.5V
V
CC
= 2.3V to 5.5V
V
CC
= 3.0V
V
CC
= 2.3V to 5.5V
V
CC
= 2.3V to 5.5V
V
CC
= 2.3V to 5.5V
V
CC
= 2.6V to 5.5V
25
0.1
0.1
0.1
5
Values
Typ
1.7
2.5
4.0
1
550
1.2
2.1
2.8
40
10
+0
+0
Max
mA
mA
mA
µA
MHz
GHz
GHz
GHz
MHz
MHz
dBm
dBm
dBm
V
V
µA
µA
µA
µA
µA
µA
mA
mA
nA
%
Units
3
www.national.com
Electrical Characteristics
Symbol
ICP
o
vs V
Do
ICP
o
vs T
V
OH
V
OL
t
CS
t
CH
t
CWH
t
CWL
t
ES
t
EW
Parameter
CP Current vs Voltage
CP Current vs Temperature
High-Level Output Voltage
Low-Level Output Voltage
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
(Continued)
V
CC
= 3.0V, V
p
= 3.0V; −40˚C
<
T
A
<
85˚C except as specified
Conditions
Min
0.5
≤
V
CPo
≤
V
p
− 0.5
T
A
= 25˚C
V
CPo
= V
p
/2
−40˚C
<
T
A
<
85˚C
I
OH
= −500 µA
I
OL
= 500 µA
50
10
50
50
50
50
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
See Data Input Timing
V
CC
− 0.4
0.4
Values
Typ
5
5
Max
%
%
V
V
ns
ns
ns
ns
ns
ns
Units
Clock to Load Enable Set Up Time
Load Enable Pulse Width
Note 3:
See PROGRAMMABLE MODES for ICP
o
description
Note 4:
Except f
IN
and OSC
IN
.
www.national.com
4
Charge Pump Current Specification Definitions
DS100127-3
I1
= CP sink current at V
CPo
= V
p
–∆V
I2
= CP sink current at V
CPo
= V
p
/2
I3
= CP sink current at V
CPo
=
∆V
I4
= CP source current at V
CPo
= V
p
–∆V
I5
= CP source current at V
CPo
= V
p
/2
I6
= CP source current at V
CPo
=
∆V
∆V
= Voltage offset from positive and negative rails. Dependent on VCO tuning range relative to V
CC
and ground. Typical values
are between 0.5V and 1.0V
1.
ICP
o
vs V
CPo
= Charge Pump Output Current magnitude variation vs Voltage =
2.
3.
[
1
⁄
2
*
{ |I1| − |I3|}]/[
1
⁄
2
*
{|I1| + |I3|}]
*
100% and [
1
⁄
2
*
{|I4| − |I6|}]/[
1
⁄
2
*
{|I4| + |I6|}]
*
100%
ICP
o-sink
vs ICP
o–source
= Charge Pump Output Current Sink vs Source Mismatch =
[|I2| − |I5|]/[
1
⁄
2
*
{|I2| + |I5|}]
*
100%
ICP
o
vs T = Charge Pump Output Current magnitude variation vs Temperature =
[|I2
@
temp| − |I2
@
25˚C|]/|I2
@
25˚C|
*
100% and [|I5
@
temp| − |I5
@
25˚C|]/|I5
@
25˚C|
*
100%
5
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