lab 3.docx

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library IEEE;

use IEEE.std_logic_1164.all;

entity uklad1 is

port(a,b,c,d : in std_logic;

Y1,Y2 : inout std_logic;

y : out std_logic);

end uklad1;

architecture uklad1 of uklad1 is

begin

Y1 <= a and b;

Y2 <= c and d;

y <= Y1 or Y2;

end uklad1;

library IEEE;

use IEEE.std_logic_1164.all;

entity uklad is

port(A,B,C,D : in std_logic;

Y : out std_logic);

end uklad;

architecture structure of uklad is

component uklad1 is

port(a,b,c,d : in std_logic;

Y1, Y2 : inout std_logic;

y : out std_logic);

end component;

begin

uklad: uklad1 port map (a=>A, b=>B, c=>C, d=>D, y=>Y);

end structure;