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19-1152; Rev 0; 10/96
MAX1114/MAX1125 Evaluation Kit
_______________General Description
The MAX1114/MAX1125 Evaluation Kit (EV kit) is a tool
for the evaluation and characterization of the MAX1114
(150MHz) or MAX1125 (300MHz) analog-to-digital con-
verters (ADCs).
The evaluation board’s dimensions are 7.562" x 8.125".
It consists of several electrical sections, each of which
is explained in the
Detailed Description:
• Power connections
• Reference circuit
• Analog input circuit
• MAX1114/MAX1125 ADC
• Clock driver/divider circuit
• Digital output latches
____________________________Features
o
o
o
o
o
150MHz/300MHz Conversion Rate
On-Board Reference Circuit
AC-Coupled Input
Clock-Input/Divider Circuit
On-Board Reconstruction DAC
Evaluates: MAX1114/MAX1125
______________Ordering Information
PART
MAX1114 EVKIT
MAX1125 EVKIT
TEMP. RANGE
0°C to +70°C
0°C to +70°C
BOARD TYPE
PGA (with MAX1114)
PGA (with MAX1125)
________________________Applications
Digital Oscilloscopes
Transient Capture
Radar, EW, ECM
Direct RF Down-Conversion
Medical Electronics
_______________________________________________________________Block Diagram
ANALOG IN
VIN
C
R
VOS
J1
VIN
8
DATA
LATCHES
8
16
DB37
CONNECTOR
2
MAX1114
MAX1125
DOUT
BUFFER
REFERENCE
CIRCUIT
VRBF
VRBS
VR1
VR2
VR3
VRTS/F
CLK
DR
8
CLK
DIVIDER
CIRCUIT
(1/2, 1/4,
1/8, 1/16)
3
RECONSTRUCTION
DAC
OUT+
COMP
CLK
CLOCK
DISTRIBUTOR
OUT-
J7
V+
V-
+5V
AGND
-5.2V
SELECT
SWITCHES
GND
-D4.5V
________________________________________________________________
Maxim Integrated Products
1
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX1114/MAX1125 Evaluation Kit
Evaluates: MAX1114/MAX1125
____________________Component List
DESIGNATION
QTY
DESCRIPTION
C1, C2, C3
3
10µF, 25V, 20% tantalum capacitors
C4–C22,
21 4.7µF, 16V, 20% tantalum capacitors
C100, C101
C28
1
0.01µF ceramic capacitors
C29, C30–C51,
0.1µF ceramic capacitors
C53–59, C61,
46
C63–C72, C87, C88,
C89, C903, C904
C80–C86,
C800, C801
D1
D2–D5
FB1–FB9
P1
Q1, Q2
R1, R3, R4
R2
R5–R9
R10–R13
R14, R15
R16, R17, R18
R19–R24
R25–R29
R30
R31
R32
R38–R46, R48–R62,
R65–R73
RN1, RN2
RN3–RN7
RN8
RN9
SW1, SW2, SW3
U1
U2
U3
U4
U5, U13
U6, U7
U8
U9
U10
U11, U12, U13, U14
N/A
N/A
N/A
N/A
N/A
2
9
1
4
9
1
2
3
1
5
4
2
3
6
5
1
1
1
33
2
5
1
1
3
1
1
1
1
2
2
1
1
1
4
5
4
8
4
13
100pF ceramic capacitors
3.9V zener diode 1N5228
Diodes 1N4001
Ferrite beads
DB37 connector
Transistors 2N2907
51Ω, 1/8W, 5%, carbon-film resistors
22Ω, 1/8W, 5%, carbon-film resistor
200Ω potentiometers
1kΩ potentiometers
120Ω chip resistors
2kΩ chip resistors
1kΩ chip resistors
22Ω chip resistors
200Ω chip resistor
5.1kΩ chip resistor
390Ω chip resistor
49.9Ω chip resistors
16 DIP, 47Ω resistor networks
6 SIP, 51Ω resistor networks
8 SIP, 51Ω resistor network
10 SIP, 51Ω resistor network
Single-pole, double-throw switches
DUT, MAX1114 or MAX1125 46L PGA
Op amp
Op amp (quad)
Comparator
Regulators
Hex flip-flops
Counter
Multiplexer
Digital-to-analog converter
XOR Gates
Banana jacks
BNC connectors
Pin sockets
Spacers
Test points
_______________Detailed Description
Analog Inputs
The analog signal is input via the V
IN
BNC connector.
It is AC coupled and level shifted by a -1V offset. The
AC coupling is provided by C28 (0.01µF) in parallel
with C29 (0.1µF). The AC-coupled signal is level shifted
though the 49.9Ω resistor R2 (Figure 6).
The -1V offset voltage can be internally supplied by
putting a jumper at J1, or it can be externally supplied
through test point V
OS
by leaving jumper J1 open.
The on-board offset is generated by D1, which is a
3.9V zener diode. R11 is a voltage-divider adjustment
potentiometer that feeds the adjusted -1V reference
into buffer U2 and drives the Q1 emitter follower to pro-
vide the final offset voltage.
Note that the MAX1114/MAX1125 EV board provides
no voltage input protection for the analog input. Take
care to ensure that the input voltage does not exceed
the device’s absolute maximum input rating, which is
from (V
EE
- 0.7V) to (GND + 0.7V).
Reference Circuits
The reference ladder top input pins, VRTF (force) and
VRTS (sense), should be 0.0V. VRTF and VRTS are
tied directly to ground through jumpers J5 and J6, respec-
tively. To drive these pins with active force and sense,
build this circuitry in the prototype area provided on the
board. With J5 and J6 removed, inject the force and
sense directly into test points VRTF and VRTS. See the
MAX1114 or MAX1125 data sheet for the recommended
force and sense circuit.
Table 1. Ladder Adjust Points
TEST POINT
VRBF
VR1
VR2
VR3
ADJUST
R10
R7
R8
R9
SET POINT
±5mV
-2.0V
-1.5V
-1.0V
-0.5V
Table 2. Power-Supply Requirements
POWER
SUPPLY
-5.2V Analog
+5.0V Analog
-4.5V Digital
MIN
-5.1
+4.9
-5.1
TYP
-5.2
+5.0
-5.2
MAX
-5.3
+5.1
-5.3
TYP CURRENT
REQUIREMENT
500mA
20mA
1A
_______________________________________________________________________________________
MAX1114/MAX1125 Evaluation Kit
The same diode described above, D1 (3.9V zener
diode), is used in conjunction with voltage divider R10
(1kΩ potentiometer) to generate the on-board reference
for the bottom of the reference ladder. R10 adjusts the
reference level, and the voltage is buffered through
U3A and fed into the bottom of the ladder force and
sense through the Q2 emitter follower. R31 (5.1kΩ)
closes the loop to prevent U3A’s output from going to
the rail when the analog-to-digital converter (ADC)
is removed.
It is critical that the reference voltage not exceed the
absolute maximum rating. U3 is a rail-to-rail op amp,
and is supplied from ground to -5.2V. It is very impor-
tant that this op amp’s output not go above 0.0V.
Reference circuit U3A is self-protected to prevent going
above ground or below -V
EE
.
It is highly recommended that each reference pin be
decoupled with three capacitors in parallel. A 100pF
chip capacitor should be closest to the converter, fol-
lowed by a 0.01µF chip capacitor, and then a 2µF to
10µF tantalum capacitor.
Evaluates: MAX1114/MAX1125
Driving Additional Ladder Taps
The MAX1114/MAX1125 CERQUAD package version
provides additional pins for driving the 1/4-, 1/2-, and
3/4-scale ladder taps. Only a 1/2-scale ladder-tap pin is
provided for the MAX1114/MAX1125 ceramic SB pack-
age version. The reference ladder taps can be used to
improve the linearity of the converter and tracking over
temperature.
The MAX1114/MAX1125 EV kit uses a PGA version of
the part that provides all three taps. The voltage refer-
ence source for all three taps is derived from a voltage
divider connected between VRBF and VRTF with four
resistors: R20, R21, R22, and R23; and three poten-
tiometers: R7, R8, and R9. Avoid using potentiometers
in an actual application design, because they have a
very poor temperature coefficient (TC). The resistors
used in a design should be ratio matched to 0.1%
or better (i.e., 1/4LSB), and track each other over
temperature.
R7 is the adjustment potentiometer for the 3/4-scale tap
(typically -1.5V); R8 is for the 1/2-scale tap (typically
-1.0V); and R9 is for the 1/4-scale tap (typically -0.5V).
These voltages are buffered through U3B, U3C, and
U3D, respectively. Jumpers J2, J3, and J4 are the
jumper options for VR1, VR2, and VR3, respectively.
The jumpers should be configured according to the
desired setup.
Converter Power Supply
The MAX1114/MAX1125 require a single -5.2V (V
EE
)
power supply, which is supplied through a total of six
pins in the PGA package. Due to the distribution of sup-
ply pins on the PGA package, the supply decoupling
on the MAX1114/MAX1125 EV kit board is divided into
four pin groups (Figure 6). The four groups comprise a
single H1 pin, a single G8 pin, pins C1 and E2, and
pins C9 and E9.
Each group is decoupled with three capacitors in paral-
lel. A 100pF chip capacitor should be closest to the
converter, followed by a 0.01µF chip capacitor, and
then a 2µF to 10µF tantalum capacitor.
Board Layout
The MAX1114/MAX1125 EV kit is built on a six-layer PC
board with 10mil signal lines. These lines are 50Ω con-
trolled impedance. Layer assignments are as follows:
Layer 1: Signal lines (controlled impedance)
Layer 2: Ground layer
Layer 3: Ground layer
Layer 4: Power layer
Layer 5: Ground layer
Layer 6: Signal lines (controlled impedance)
Analog and digital ground share the same ground
layer. All supplies share the same power layer.
5V SUPPLY
+
-
5.2V SUPPLY
+
-
4.5V SUPPLY
+
-
ANALOG
GROUND PLANE
FERRITE BEAD
DIGITAL
GROUND PLANE
MAX1114/
MAX1125
+5V
ANALOG
AGND
-5.2V DGND
ANALOG
-4.5V
DIGITAL
AGND
+5V
ANALOG
-5.2V
-4.5V
DIGITAL
DGND
MAX1114/MAX1125EVKIT
Figure 1. Power-Supply Hookup
Figure 2. Power and Ground Distribution
3
_______________________________________________________________________________________
MAX1114/MAX1125 Evaluation Kit
Evaluates: MAX1114/MAX1125
Table 3. Data Ready Output Decimation Table
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Logic Zero
or No Clock
DECIMATED
OUTPUT
÷1
÷2
÷4
÷8
÷16
-5.2V
CLK IN
(DIFFERENTIAL)
ECL
2
AGND
8
7
CLK
10EL16
3
5
6
CLK
Figure 3. Differential Input Clock
Clock-Driver Circuit
The MAX1114/MAX1125 EV kit uses a high-speed volt-
age comparator (U4A) in the clock-driver circuit,
allowing the user to drive the evaluation board directly
from a symmetrical sinewave input signal (U4B is not
used).
Comparator U4A converts the signal into a differ-
ential ECL output signal compatible with the MAX1114/
MAX1125. Driving the MAX1114/MAX1125 with a
differential clock is highly recommended because it
minimizes aperture jitter in the converter.
Note that the circuit associated with U4A is supplied
from all analog supplies: -5.2V (analog), +5.0V (analog),
and -2V pull-down voltage (analog). U4 must be sup-
plied from analog supplies to eliminate the possibility of
ground loops that may degrade the performance of the
converter. The -2V (-A2) pull-down voltage is generated
from an adjustable voltage regulator (U5).
In normal operation, jumper J7A must be installed and
J7B must be open. This achieves a 50% duty cycle for
the clock input into the converter, assuming the input
clock signal (CLK IN) is a sinewave symmetrical about
0.0V. The clock input should not exceed ±2V. (Input
compliance for U4 is ±2.5V.)
In some applications, there may be a need for a clock
duty cycle other than 50%. To test the converter perfor-
mance under these conditions, open jumper J7A and
short J7B. Adjust potentiometer R12 for the desired duty
cycle. A clock-monitoring test point is provided. The test
point looks similar to the way it is pictured in the
schematic. (It provides a short ground-path connection.)
Maxim recommends using a Motorola Eclipse Lite
MC10EL16 driver in designing your clock-driver circuit.
Figure 3 shows the MC10EL16 in a differential ECL
4
8
CLK IN
(ECL)
2
AGND
7
CLK
10EL16
3
5
4
0.1µF
AGND
-5.2V
6
CLK
Figure 4. Single Input Clock
input clock-driver configuration, and Figure 4 shows
how it is used when driving from a single-ended ECL
clock source.
Digital Outputs
The MAX1114/MAX1125’s digital outputs are immediate-
ly followed by U6 and U7 latched hex D flip-flop regis-
ters. U14C and U14D are used as gated buffers to latch
the registers using the decimated Data Ready signal
generated from U8 and U9 (Table 3.) Each of the differ-
ential outputs of U6 and U7 is split into two digital output
paths.
The first path goes to buffers U11 and U12 to provide a
differential output of the data through the P1 connector
(D shell). The second path feeds U10, a reconstruction
digital-to-analog converter (DAC). Both paths also
carry the decimated Data Ready signal generated from
U8 and U9 (Table 3).
_______________________________________________________________________________________
MAX1114/MAX1125 Evaluation Kit
Data Ready Signal
The MAX1114/MAX1125’s Data Ready signal is fed into
a four-state counter/shift register (U8). U8 divides down
(decimates) the Data Ready by 2, 4, 8, and 16.
Connecting jumper J12 to ground inverts the Data
Ready before input into the counter.
The desired decimated Data Ready signal is selected
by switches S0–S2 (Table 3). These switches select the
output from U9 (dual 8-input multiplexer) and feed it to
the two output paths described above (i.e., P1 or the
reconstruction DAC).
Both OUT+ and OUT- are current-sinking outputs, and
are loaded with 50Ω termination resistors R3 and R4.
These termination resistors are socketed and can be
removed. The load can be changed as long as the out-
put remains within the -1.2V to +1.5V output compli-
ance voltage range. The digital input format is straight
binary.
Evaluates: MAX1114/MAX1125
Jumper Options
Table 4 shows the MAX1114/MAX1125 EV kit jumper
defaults.
Table 4. Jumper Defaults*
JUMPER STATUS
J1
J2
J3
J4
J5
J6
J7A
J7B
J8
J9L
J9M
J10
J11
J12
J13
J14
J16
J17A
J17B
J18A
J18B
Short
Open
Short
Open
Short
Short
Short
Open
Open
Open
Open
Open
Open
Open
Open
Short
Short
Open
Short
Open
Short
CONFIGURATION
Internal -1V analog input level shift
VR1 reference ladder tap open
Force middle reference ladder tap VR2
VR3 reference ladder tap open
Connect VTRF to AGND
Connect VRTS to AGND
Set clock reference voltage to AGND
(J7B must be open when J7A is shorted)
DRINV to logic low
LINV to logic low
MINV to logic low
No inversion for U14C and U14D
No inversion for U14E
No inversion for DREAD
No inversion of clock signal to P1
P1, pins 33, 34, 37 to DGND
U10 (DAC) set for a fixed gain
Required jumper configuration for U10
Required jumper configuration for U10
Required jumper configuration for U10
Required jumper configuration for U10
Data Output Logic Control
The MAX1114/MAX1125 EV kit provides options for
inverting the MSB, LSB, and Data Ready outputs
via output control pins MINV, LINV, and DRINV, respec-
tively. These pins are internally tied low inside the
MAX1114/MAX1125. They may be tied high using
jumpers J8 (for DRINV), J9L (for LINV), and J9M (for
MINV). The MAX1114 or MAX1125 data sheet shows
the output coding table as a function of these output
control pins.
NOTE: The reconstruction DAC (U10) requires a
straight binary digital input format.
Board Power Supplies and Grounding
The MAX1114/MAX1125 EV kit requires three externally
supplied power supplies: +5V analog, -5.2V analog,
and -4.5V digital.
In addition, a -2V pull-down supply is generated from
digital -4.5V using an adjustable voltage regulator
(U13). The analog and digital ground planes are kept
separate and are tied together through a ferrite bead as
close to the ADC as possible (Figure 2).
Reconstruction DAC
U10 is an 8-bit, high-performance reconstruction DAC.
U10 is set for a fixed gain when jumper J16 is installed,
or can be adjusted by removing J16 and using poten-
tiometer R13.
*An
additional 10 jumpers are shipped with the board.
_______________________________________________________________________________________
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