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19-1191; Rev 0; 6/97
MAX1170 Evaluation Kit
_______________General Description
The MAX1170 evaluation kit (EV kit) evaluates the per-
formance of the MAX1170/MAX1171/MAX1172 mono-
lithic, 12-bit high-speed analog-to-digital converters
(ADCs). The ADCs must be ordered separately.
The MAX1170/MAX1171/MAX1172 have ±2V analog
input ranges. They can digitize an analog input signal
into 12-bit words at minimum update rates of 10Msps,
20Msps, and 30Msps, respectively.
____________________________Features
o
Up to 30Msps Conversion Rate
o
On-Board Clock Drivers
o
Data Output and Strobe Signal
o
User-Selectable Capture Clock
o
On-Board Reference Drivers
Evaluates: MAX1170/MAX1171/MAX1172
________________EV Kit Applications
Evaluation of MAX1170/MAX1171/MAX1172
Engineering System Prototype Aid
Incoming Inspection Tool
Guide for System Layout
______________Ordering Information
PART
MAX1170EVKIT*
TEMP. RANGE
0°C to +70°C
*Evaluates
either MAX1170CDJ, MAX1171CDJ, or MAX1172CDJ,
which must be ordered separately.
MAX1170
MAX171
MAX1172
THE MAX1170 EV KIT CONSISTS OF FIVE SEPARATE SECTIONS:
1) REFERENCE CIRCUITS
2) CLOCK CIRCUITS
3) MAX1170, MAX1171, OR MAX1172 12-BIT ADC (NOT INCLUDED WITH THE BOARD)
4) OUTPUT LATCHES AVAILABLE THROUGH A 26-PIN FEMALE RIBBON CONNECTOR
5) THE DAC RECONSTRUCTION BOARD IS A SEPARATE DAUGHTERBOARD (2.5" x 3.0") THAT INTERFACES DIRECTLY WITH THE MAX1170 EV KIT MAIN BOARD (4" x 7.5")
Figure 1. Functional Diagram
________________________________________________________________
Maxim Integrated Products
1
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX1170 Evaluation Kit
Evaluates: MAX1170/MAX1171/MAX1172
___________________________________________MAX1170 EV Kit Component List
DESIGNATION QTY
C1–C7, C10
C20, C30
C21–C29,
C31, C32
C50–C58
D1
FB1, FB2, FB3
None
P1
P1/Receptacle
P2, P3
PJ1, PJ2
R1, R2
R3
R10, R11, R12
R20, R21
R26, R27, R30
R28
8
2
11
9
1
3
1
1
1
2
2
2
1
3
2
3
1
DESCRIPTION
10µF, 25V, 0.10" tantalum capacitors
0.1µF chip capacitors
0.01µF chip capacitors
0.01µF, 10% ceramic capacitors
Lead-mounted hot-carrier diode
Lead-mounted ferrite beads
Printed circuit board
9-pin power connector
9-pin power-connector, receptacle
Ribbon-plug connectors
Probe connectors
10kΩ, 12-turns potentiometers
2kΩ, 12-turns potentiometer
51Ω, 5%, 1/8W resistors
820Ω, 5%, 1/8W resistors
20kΩ, 5%, 1/8W resistors
1MΩ, 5%, 1/8W resistor
DESIGNATION QTY
R32
R33
RN1, RN2
TP1, TP2, TP3,
AG, DG, STEP
U1
U2
U3
U5
U7, U8
None
None
None
None
None
None
None
1
1
2
6
1
1
1
1
2
3
1
1
4
4
1
8
DESCRIPTION
5.1kΩ, 5%, 1/8W resistor
10kΩ, 5%, 1/8W resistor
10kΩ, 708A-type, 8-pin SIP resistors
76-mil-diameter hole test-point
terminals
Device under test: 12-bit ADC
+2.5V precision voltage reference
Low-noise op amp
Single, fast-TTL comparator (8 DIP)
Fast TTL, hex D flip-flops
BNC connector, receptacles
0.600" socket (32 DIP)
Break-away socket strips (20 SIP)
1" round nylon standoffs
3/16", 4-40, round-head nylon screws
Crimp male terminal for P3
Crimp female terminals for P3
____________________________________________Daughterboard Component List
DESIGNATION QTY
C1, C2
C10–C16
C21–C25
D1
DB792 PCB
FB1, FB2
P2, P3
R1
R2
R3
R4
R5
2
7
5
1
1
2
2
1
1
1
1
1
DESCRIPTION
10µF, 25V, 0.10" tantalum capacitors
0.1µF chip capacitors
0.1µF, 10% ceramic capacitors
1.2V reference, 2-terminal IC
Printed circuit board
Lead-mounted ferrite beads
26-pin, dual-row, vertical PCB-mount
connectors
10kΩ, 12-turns potentiometer
7.5kΩ, 5%, 1/8W resistor
22Ω, 5%, 1/8W resistor
10kΩ, 5%, 1/8W resistor
15kΩ, 5%, 1/8W resistor
DESIGNATION QTY
R6
R7
R8
R11, R12
R20, R21
R22
TP1, AG, DG
U9
U10
U11
—
—
1
1
1
2
2
1
3
1
1
1
1
1
DESCRIPTION
20kΩ, 5%, 1/8W resistor
1kΩ, 5%, 1/8W resistor
1kΩ, 5%, 1/8W resistor
150Ω, 5%, 1/8W resistors
820Ω, 5%, 1/8W resistors
200Ω, 5%, 1/8W resistor
76-mil-diameter hole, test-point
terminals
100MHz, 12-bit TTL DAC
Low-noise op amp
Low-distortion op amp
BNC connector
Crimp male terminal for P3
2
_______________________________________________________________________________________
MAX1170 Evaluation Kit
_______________Detailed Description
Power Supplies
The MAX1170/MAX1171/MAX1172 require four power-
supply sources: analog -5.2V (-A5.2V), analog
+5V (+A5V), digital -5.2V (-D5.2V), and digital +5V
(+D5V). P1 is the power connector (Figure 2). Table 1
shows the recommended operating voltage range.
AGND and DGND are isolated on the MAX1170/
MAX1171/MAX1172. Both -A5.2V and +A5V are the
analog supply sources. As with all very-high-speed
ADCs, grounding is critical. Therefore, the ground-
plane technique is best. To use this method, split and
tie the AGND and DGND ground planes together at the
device through an RF bead.
The MAX1170 EV kit is a four-layer printed circuit
board: top signal, ground (AGND and DGND) plane,
power plane, and bottom signal. The two ground
planes are connected at the device through a ferrite
bead (RF3). All three ferrite beads (RF1, RF2, and RF3)
are located close to the ADC.
Evaluates: MAX1170/MAX1171/MAX1172
Power Supplies and Grounding
The MAX1170/MAX1171/MAX1172 require two analog
supply voltages: -A5.2V and +A5V. The +A5V supply is
common to analog VCC (pins 20 and 29) and digital
DVCC (pins 16 and 32). A ferrite bead in series with
each supply (RF1 and RF2) reduces the transient noise
injected into VCC. The bead to MAX1170/MAX1171/
MAX1172 connections should not be shared with any
other device. Bypass each power-supply pin as closely
as possible to the device (0.1µF to AGND for each VEE
and VCC pin, and 0.01µF to DGND for DVCC).
Total power dissipation for the MAX1170 EV kit is typi-
cally 1.9W.
Table 1. Recommended Power-Supply
Operating Range
POWER
SUPPLY
(V)
-A5.2
+A5
-D5.2
+D5
MIN
(V)
-4.95
+4.75
-4.95
+4.75
TYP
(V)
-5.20
+5.00
-5.20
+5.00
MAX
(V)
-5.45
+5.25
-5.45
+5.25
TYPICAL
CURRENT
(mA)
60
240
15
60
Figure 2. P1 Power-Supply Connector’s Pin Assignment
Table 2. Pin Assignments
PIN
1
2
3
4
5
6
7
8
9
DESCRIPTION
Analog -5.2V
Analog -5.2V Return #1 (AGND)
Analog -5.2V Return #2 (AGND)
Analog +5V
Analog +5V Return (AGND)
Digital -5.2V Return (DGND)
Digital +5V
Digital +5V Return (DGND)
Digital -5.2V
2
3
1
4
5
6
9
7
8
-5.2 V
+
-
+5V
+
-
- 5.2 V
+
-
+5V
+
-
P1 POWER CONNECTOR
Figure 3. P1 Connector/Hookup
_______________________________________________________________________________________
3
MAX1170 Evaluation Kit
Evaluates: MAX1170/MAX1171/MAX1172
Reference Circuit
The MAX1170/MAX1171/MAX1172 require the use of
two voltage references: VFT and VFB. VFT (+2.5V typ)
is the force for the top of the voltage-reference ladder,
and VFB (-2.5V typ) is the force for the bottom of the
voltage-reference ladder. Both voltages are applied
across an internal 900Ω reference-ladder resistance. In
addition, there are five reference-ladder taps: VST,
VRT3, VRT2, VRT1, and VSB. VST (+2V) is the top of
the reference-ladder tap; (+2V), VRT3 (+1.0V typ) is the
top half of the ladder; VRT2 (0V typ) is the middle point;
VRT1 (-1.0V) is the bottom half; and VSB (-2V) is the
bottom of the reference-ladder tap. The voltages at VST
and VSB are the full-scale input voltages expected of
the device when VFT and VFB are driven to the recom-
mended voltages (typically +2.5V and -2.5V, respec-
tively). Use VST and VSB (±2V) to monitor the actual
full-scale input voltages by adjusting VFT and VFB
(Table 3). These adjustments interact with one another;
repeat them several times as needed until VST and
VSB settle at the desired voltages. Do not drive the
three taps (VRT1, VRT2, and VRT3), as is commonly
done with a standard flash ADC converter. When not
being used, decouple with a 0.01µF, surface-mount
chip capacitor from each tap to AGND, to minimize
high-frequency noise injection.
As shown in Figure 17, U2 is the +2.5V reference with
±0.6% of adjustable range (R1 potentiometer). U3 is set
up as an inverting amplifier. Its tolerance is 5% with
±300mV of adjustable range (R2 potentiometer). Maxim
recommends that you operate VFT and VFB to within
±2% (or ±2.5V ±50mV) to maintain accuracy within the
specified limit. Before each MAX1170 EV kit board is
shipped, the references are adjusted to ±2.5V ±5mV.
For each new MAX1170/MAX1171/MAX1172, readjust
VST and VSB. All measurements must be referenced to
the AGND test point provided.
Figure 17 shows one type of reference driver. Figure 4
shows another way to drive the reference circuits using
force and sense. This circuit provides better control on
the plus full-scale (+FS) and minus full-scale (-FS)
errors by sensing VST and VSB to ±2.0V, respectively.
However, VST and VSB are not low-impedance nodes;
thus, they require additional precaution when routing
(PCB layout).
ADCs
The MAX1170 is a 12-bit ADC capable of digitizing an
input signal with a 10Msps update rate. The
MAX1171/MAX1172 ADCs are pin compatible with the
MAX1170, but digitize two and three times faster,
respectively. On all devices, the expected full-scale
analog input range is from VST to VSB. The analog
input is latched at CLK’s leading edge. There are 13
digital TTL outputs. D0–D11 are the parallel TTL output
bits, with D0 the least significant bit (LSB), D11 the
most significant bit (MSB), and D12 the overrange bit.
The data outputs are latched at CLK’s rising edge, with
a 14ns typical propagation delay. There is one clock
latency between CLK and valid output data (Figure 5).
The output code is straight binary.
Table 3. Reference Adjustment
VST
Test Point
Min
Typ
Max
Adjust
U1, pin 21
+1.950V
+2.000V
+2.050V
R1
VSB
U1, pin 27
-2.050V
-2.000V
-1.950V
R2
NOTE: The MAX1170/MAX1171/MAX1172 (especially all refer-
ence taps) are sensitive to electrostatic discharge (ESD).
Table 4. Output Coding
ANALOG INPUT
<-2.0V
-2.0V + 1LSB
0V
+2.0V - 1LSB
>+2.0V + 1/2LSB
D12
(OVERRANGE
BIT)
0
0
0
0
1
DATA
OUTPUT CODE
0000 0000 0000
0000 0000 000Ø
ØØØØ ØØØØ ØØØØ
1111 1111 111Ø
1111 1111 1111
+2.5V REF
NOTE: Ø indicates the flickering bit between logic 0 and 1.
4
Figure 4. Alternative Reference Driver
_______________________________________________________________________________________
MAX1170 Evaluation Kit
Evaluates: MAX1170/MAX1171/MAX1172
≤
6nS
Figure 5. Digital Output Characteristic of the MAX1170/MAX1171/MAX1172
Pin 24 is the analog input pin. Selecting the analog
input driver is simpler than with most flash ADCs
because the input impedance and input capacitance
are typically 300kΩ and 5pF, respectively. For example,
at 5MHz and 4Vp-p sine-wave input, the input driver
source requires only 0.324mA of peak output current
(4πFC).
The analog input is fed directly from a BNC (VIN). R10
(51Ω) is the analog input source termination mounted on
a socket as a user-selectable termination. The analog
input pin has no circuit protection. Its maximum rating is
from VFT to VFB (±2.5V). Use a voltage limiter to protect
the input pin from permanent damage in applications
with an analog input range greater than ±2.5V (see the
Input and Latchup Protection
section).
Input Clock Driver
CLK is the single-ended input clock to the MAX1170 EV
kit; CLK IN is the input clock to the ADC; and CCLK is the
capture clock used for the output latches (U7 and U8).
The MAX1170/MAX1171/MAX1172’s clock input
requires TTL-logic level with a 6ns or faster rise time to
reduce noise. Fast TTL-family components (74FXX) fit
well in this application. Finding a square-wave genera-
tor (TTL logic up to 30MHz, fast slew rate, and low jitter)
is more difficult than finding a sine-wave, low-jitter gen-
erator. U5 (MAX9686, TTL voltage comparator) pro-
vides most of the above requirements for driving the
ADC (except the low-jitter generator). The CLK signal
should be a sine-wave signal with an amplitude not to
exceed ±3V (input common-mode limitation of U5). R11
(51Ω) is the CLK source termination. Use R3 to adjust
the CLK IN duty cycle. CLK IN is in phase with CLK
and with a 6ns typical propagation delay. Due to the
internal track/hold amplifier (THA), keep the positive
clock (CLK IN) pulse width from 15ns to 300ns for the
MAX1172, 20ns to 300ns for the MAX1171, and 30ns to
300ns for the MAX1170. When operating the ADC
faster than 3Msps, keep the clock duty cycle at approx-
imately 50% ±10%. Probe jack PJ1 is the monitoring
test point for CLK IN. Use this test point when adjusting
the clock duty cycle.
A falling edge at CLK IN (pin 17) causes the internal
THA to go into track mode. Keep the MAX1170/
MAX1171/MAX1172 in track mode at startup time or
when the device is idle for an extended period of time.
This setup prevents the internal THA from going into
saturation due to droop. The EV board provides a logic
low to the ADC clock when the pulse generator (CLK) is
removed from the evaluation board.
5
_______________________________________________________________________________________

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