2229.PDF

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DS2229
Word-Wide 8 Meg SRAM Stik
www.dalsemi.com
FEATURES
Organized as a high density 512k x 16 bit
Stik
TM
Fast access time of 85 ns
Unlimited write cycles
Employs popular JEDEC standard 80-position
SIMM connector
Full
±10%
operating range
Read cycle time equals write cycle time
Ultra-low standby current < 10
µA
Suitable for battery-backed applications
PIN ASSIGNMENT
1
1M
SRAM
1M
SRAM
1M
SRAM
1M
SRAM
80-PIN SIP STIK
80
DESCRIPTION
The DS2229 is an 8,388,608-bit low-power fully static Random Access Memory organized as a 524,888
word by 16 bits using CMOS technology. The device employs the popular JEDEC standard 80-pin SIMM
connection scheme with no additional circuitry required. The device operates from a single power supply
with a voltage input of 4.5 to 5.5 volts. The Chip Enable inputs (
CE0
,
CE1
,
CE2
,
CE3
) are used for
device selection and can be used in order to achieve the minimum standby current mode which facilitates
battery backup. The device provides a fast access time of 85 ns. The DS2229 maintains TTL levels over
input voltage range 4.5V to 5.5V. The DS2229 is JEDEC pin compatible (see Figure 1) with flash
EEPROM memory SIMM boards of similar density.
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112099
DS2229
PIN DESCRIPTION
Figure 1
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PIN NAME
GND
V
CC
NC
OE
WEH
WEL
PIN #
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
PIN NAME
NC
NC
NC
NC
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
GND
GND
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
PIN #
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
PIN NAME
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
NC
V
CC
NC
GND
NC
GND
GND
NC
NC
GND
NC
CS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
CE3
CE2
CE1
CE0
PIN NAME
A
0
- A
16
WEL
WEH
OE
DESCRIPTION
Address Input
Write Enable Input Low
Write Enable Input High
Output Enable Input
No Connect
Chip Enable Input
Chip Select
Data Input/Output
+5 Volts
Ground
GND
NC
NC
NC
NC
NC
NC
NC
CE0
-
CE3
CS
DQ
0
- DQ
15
V
CC
GND
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DS2229
DS2229 STATIC RAM MODULE FUNCTION DIAGRAM
Figure 2
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DS2229
ABSOLUTE MAXIMUM RATINGS*
Power Supply Voltage
Input, Input/Output Voltage
Operating Temperature
Storage Temperature
*
-0.3V to +7.0V
-0.3 to V
CC
+0.3V
0°C to 70°C
-55°C to +125°C
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
OPERATION MODE
MODE
READ
WRITE
DESELECT
STANDBY
STANDBY
CE0
-
CE3
CS
H
H
H
X
L
OE
WE
A0 - A16
STABLE
STABLE
X
X
X
DQ - DQ15
DATA OUT
DATA IN
HIGH-Z
HIGH-Z
HIGH-Z
POWER
I
CC0
I
CC0
I
CC0
I
CCS1
, I
CCS2
I
CCS1
, I
CCS2
L
L
L
H
X
L
X
H
X
X
H
L
H
X
X
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
C
IN
C
I/O
MIN
TYP
MAX
64
80
(t
A
=25°C)
UNITS
pF
pF
NOTES
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Power Supply Voltage
Input High Voltage
Input Low Voltage
SYMBOL
V
CC
V
IH
V
IL
MIN
4.5
2.0
-0.3
TYP
5.0
MAX
5.5
(t
A
= 0°C to 70°C)
UNITS
V
V
V
NOTES
V
CC
+0.3
0.8
DC CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
Output High Current
Output Low Current
Standby Current
Standby Current
Operating Current
SYMBOL
I
IL
I
LO
I
OH
I
OL
I
CCS1
I
CCS2
I
CCO
CE0
CE0
(t
A
= 0°C to 70°C; V
CC
= 5V
±
10%)
CONDITIONS
0V
≤
V
IN
≤
V
CC
CE0
MIN
MAX
8
8
UNITS
µA
µA
mA
mA
NOTES
-
CE3
= V
IH
,
0V
≤
V
I/O
≤
V
CC
V
OH
= 2.4V
V
OL
= 0.4V
-
CE3
=2.0V t
A
=25°C
-
CE3
≥
V
CC
-0.3V
t
A
=25°C
-1.0
2.1
8
10
100
mA
µA
mA
9
-
CE3
= 0.8V;
Cycle=100 ns t
A
=25°C
CE0
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DS2229
LOW VCC DATA RETENTION CHARACTERISTICS
PARAMETER
V
CC
for Data Retention
SYMBOL
V
DR
MIN
2.0
TYP
-
MAX
-
UNITS
V
(t
A
= 0°C to 70°C)
TEST CONTIDION
CE0
-
CE3
≥
V
CC
-0.2V,
CS
≥
V
CC
-0.2V or 0V
≤
CS
≤
0.2V V
IN
≥
0V
V
CC
= 3.0V, V
IN
≥
0V
CE0
-
CE3
≥
V
CC
-0.2V,
CS
≥
V
CC
-0.2V or 0V
≤
CS
≤
0.2V t
A
=25°C
See Retention
Waveform
Data Retention Current
I
CCDR
-
1
8
µA
Chip Deselect to Data
Retention Time
Operation Recovery Time
t
CDR
t
R
0
5
-
-
-
-
ns
ms
LOW V
CC
DATA RETENTION TIMING WAVEFORM (1)
(
CE0
-
CE3
Controlled)
Figure 3
SEE NOTE 5
LOW V
CC
DATA RETENTION TIMING WAVEFORM (2)
(CS Controlled) Figure 4
SEE NOTE 5
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