2153Q.PDF

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DS2153Q
E1 Single-Chip Transceiver
www.dalsemi.com
FEATURES
§
Complete E1(CEPT) PCM-30/ISDN-PRI
transceiver functionality
§
Onboard line interface for clock/data recovery
and waveshaping
§
32-bit or 128-bit jitter attenuator
§
Generates line build-outs for both 120-ohm
and 75-ohm lines
§
Frames to FAS, CAS, and CRC4 formats
§
Dual onboard two-frame elastic store slip
buffers that can connect to backplanes up to
8.192 MHz
§
8-bit parallel control port that can be used on
either multiplexed or non-multiplexed buses
§
Extracts and inserts CAS signaling
§
Detects and generates Remote and AIS alarms
§
Programmable output clocks for Fractional
E1, H0, and H12 applications
§
Fully independent transmit and receive
functionality
§
Full access to both Si and Sa bits
§
Three separate loopbacks for testing
§
Large counters for bipolar and code
violations, CRC4 code word errors, FAS
errors, and E bits
§
Pin-compatible with DS2151Q T1 Single-
Chip Transceiver
§
5V supply; low power CMOS
§
Industrial grade version (-40° to +85°
C
C)
available (DS2153QN)
PIN ASSIGNMENT
FUNCTIONAL BLOCKS
LONG & SHORT
HAUL LINE
INTERFACE
PARALLEL CONTROL
PORT
DALLAS
DS2153Q
E1 SCT
ACTUAL SIZE OF 44-PIN PLCC
CS
RD
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
TCHCLK
6
5
4
3
2
1
44
43
42
41
18
19
20
21
22
23
24
25
26
27
FRAMER
DESCRIPTION
The DS2153Q T1 Single-Chip Transceiver (SCT) contains all of the necessary functions for connection
to E1 lines. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ
serial stream. The DS2153 automatically adjusts to E1 22 AWG (0.6 mm) twisted-pair cables from 0 to
1.5 km. The device can generate the necessary G.703 waveshapes for both 75-ohm and 120-ohm cables.
The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit
or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data
stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa-bit information.
The device contains a set of 71 8-bit internal registers which the user can access to control the operation
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070299
RCHBLK
ACLKI
BTS
RTIP
RRING
RVDD
RVSS
XTAL1
XTAL2
INT1
INT2
28
ALE
WR
RLINK
RLCLK
DVSS
RCLK
RCHCLK
RSER
RSYNC
RLOS/LOTC
SYSCLK
40
ELASTIC
STORES
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
TSER
TCLK
DVDD
TSYNC
TLINK
TLCLK
TCHBLK
TRING
TVDD
TVSS
TTIP
DS2153Q
of the unit. Quick access via the parallel control port allows a single micro to handle many E1 lines. The
device fully meets all of the latest E1 specifications, including ITU G.703, G.704, G.706, G.823, and
I.431 as well as ETSI 300 011, 300 233, TBR 12 and TBR 13.
TABLE OF CONTENTS
1. Introduction
2. Parallel Control Port
3. Control and Test Registers
4. Status and Information Registers
5. Error Count Registers
6. Sa Data Link Control and Operation
7. Signaling Operation
8. Transmit Idle Registers
9. Clock Blocking Registers
10. Elastic Store Operation
11. Additional (Sa) and International (Si) Bit Operation
12. Line Interface Control Function
13. Timing Diagrams, Synchronization Flowchart, and Transmit flow Diagram
14. DC and AC Characteristics
1.0 INTRODUCTION
The analog AMI waveform off of the E1 line is transformer coupled into the RRING and RTIP pins of
the DS2153Q. The device recovers clock and data from the analog signal and passes it through the jitter
attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing
pattern. If needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered E1 data stream and an asynchronous backplane clock which is
provided at the SYSCLK input.
The transmit side of the DS2153Q is totally independent from the receive side in both the clock
requirements and characteristics. The transmit formatter will provide the necessary data overhead for E1
transmission. Once the data stream has been prepared for transmission, it is sent via the jitter attenuation
mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP
and TRING pins via a coupling transformer.
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DS2153Q
Reader’ Note
s
This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit
timeslots in E1 systems which are numbered 0 to 31. Timeslot 0 is transmitted first and received first.
These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is
identical to channel 1, timeslot 1 is identical to channel 2, and so on. Each timeslot (or channel) is made
up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is
the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:
FAS
CAS
MF
Si
CRC4
CCS
Sa
E-bit
Frame Alignment Signal
Channel Associated Signaling
Multiframe
International Bits
Cyclical Redundancy Check
Common Channel Signaling
Additional bits
CRC4 Error bits
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DS2153Q
DS2153Q BLOCK DIAGRAM
Figure 1-1
4 of 52
DS2153Q
PIN DESCRIPTION
Table 1-1
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
SYMBOL
AD4
AD5
AD6
AD7
RD
(DS)
CS
TYPE
I/O
DESCRIPTION
Address/Data Bus.
An 8-bit multiplexed address/data bus.
I
I
I
I
O
O
-
O
O
Read Input (Data Strobe).
Chip Select.
Must be low to read or write the port.
Address Latch Enable (Address Strobe).
A positive going edge
serves to demultiplex the bus.
Write Input (Read/Write).
Receive Link Data.
Outputs the full receive data stream including
the Sa bits. See Section 13 for timing details.
Receive Link Clock.
4 kHz to 20 kHz demand clock for the RLINK
output; controlled by RCR2. See Section 13 for timing details.
Digital Signal Ground.
0.0 volts. Should be tied to local ground
plane.
Receive Clock.
Recovered 2.048 MHz clock.
Receive Channel Clock.
256 kHz clock which pulses high during
the LSB of each channel. Useful for parallel to serial conversion of
channel data. See Section 13 for timing details.
Receive Serial Data.
Received NRZ serial data, updated on rising
edges of RCLK or SYSCLK.
Receive Sync.
An extracted pulse, one RCLK wide, is output at this
pin which identifies either frame (RCR1.6=0) or multiframe
boundaries (RCR1.6=1). If the elastic store is enabled via the
RCR2.1, then this pin can be enabled to be an input via RCR1.5 at
which a frame boundary pulse is applied. See Section 13 for timing
details.
Receive Loss of Sync/Loss of Transmit Clock.
A dual function
output. If TCR2.0=0, will toggle high when the synchronizer is
searching for the E1 frame and multiframe; if TCR2.0=1, will toggle
high if the TCLK pin has not toggled for 5
µs.
System Clock.
1.544 MHz or 2.048 MHz clock. Only used when
the elastic store functions are enabled via RCR2.1. Should be tied
low in applications that do not use the elastic store. If tied high for at
least 100
µs,
will force all output pins (including the parallel port) to
3-state.
ALE(AS)
WR
(R/
W
)
RLINK
RLCLK
DVSS
RCLK
RCHCLK
14
15
RSER
RSYNC
O
I/O
16
RLOS/LOTC
O
17
SYSCLK
I
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