21Q44.PDF

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DS21Q44
Enhanced QUAD E1 FRAMER
www.dalsemi.com
FEATURES
Four E1 (CEPT or PCM-30) /ISDN-PRI
framing transceivers
All four framers are fully independent;
transmit and receive sections of each framer
are fully independent
Frames to FAS, CAS, CCS, and CRC4 formats
Each of the four framers contain dual two–
frame elastic store slip buffers that can
connect to asynchronous backplanes up to
8.192 MHz
8–bit parallel control port that can be used
directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)
Easy access to Si and Sa bits
Extracts and inserts CAS signaling
Large counters for bipolar and code
violations, CRC4 code word errors, FAS
word errors, and E-bits
Programmable output clocks for Fractional
E1, per channel loopback, H0 and H12
applications
Integral HDLC controller with 64-byte buffers
configurable for Sa bits or DS0 operation
Detects and generates AIS, remote alarm,
and remote multiframe alarms
Pin compatible with DS21Q42 Enhanced
Quad T1 Framer
3.3V supply with 5V tolerant I/O; low power
CMOS
Available in 128–pin TQFP package
IEEE 1149.1 support
FUNCTIONAL DIAGRAM
Receive
Fram
er
Transm
it
Form
atter
FRAMER #0
FRAMER #1
FRAMER #2
FRAMER #3
Control Port
Elastic
Store
Elastic
Store
ACTUAL SIZE
QUAD
E1
FRAMER
ORDERING INFORMATION
DS21Q44T
DS21Q44TN
(0
0
C to 70
0
C)
(-40
0
C to +85
0
C)
DESCRIPTION
The DS21Q44 E1 is an enhanced version of the DS21Q43 Quad E1 Framer. The DS21Q44 contains four
framers that are configured and read through a common microprocessor compatible parallel port. Each
framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. All
four framers in the DS21Q44 are totally independent, they do not share a common framing synchronizer.
Also the transmit and receive sides of each framer are totally independent. The dual two-frame elastic
stores contained in each of the four framers can be independently enabled and disabled as required. The
device fully meets all of the latest E1 specifications including CCITT/ITU G.704, G.706, G.962, and
I.431 as well as ETS 300 011 and ETS 300 233.
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031600
DS21Q44
1. INTRODUCTION
The DS21Q44 is a superset version of the popular DS21Q43 Quad E1 framer offering the new features
listed below. All of the original features of the DS21Q43 have been retained and software created for the
original device is transferable to the DS21Q44.
New Features
Additional hardware signaling capability including:
– receive signaling reinsertion to a backplane multiframe sync
– availability of signaling in a separate PCM data stream
– signaling freezing
– interrupt generated on change of signaling data
Per–channel code insertion in both transmit and receive paths
Full HDLC controller with 64–byte buffers in both transmit and receive paths. Configurable for Sa
bits or DS0 access
RCL, RLOS, RRA, and RUA1 alarms now interrupt on change of state
8.192 MHz clock synthesizer
Ability to monitor one DS0 channel in both the transmit and receive paths
Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233
Automatic RAI generation to ETS 300 011 specifications
IEEE 1149.1 support
Functional Description
The receive side in each framer locates FAS frame and CRC and CAS multiframe boundaries as well as
detects incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If
needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered E1 data stream and an asynchronous backplane clock which is
provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048 MHz
clock or a 1.544 MHz clock. The RSYSCLK can be a burst clock with speeds up to 8.192 MHz.
The transmit side in each framer is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
E1 transmission.
Reader’s Note:
This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125 us frame,
there are 32 eight–bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and received first. These
32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is identical
to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or channel) is made up of
eight bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is
the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used:
FAS
CAS
MF
Si
Frame Alignment Signal
Channel Associated Signaling
Multiframe
International bits
CRC4
CCS
Sa
E-bit
Cyclical Redundancy Check
Common Channel Signaling
Additional bits
CRC4 Error Bits
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DS21Q44
DS21Q44 ENHANCED QUAD E1 FRAMER
Figure 1-1
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DS21Q44
TABLE OF CONTENTS
1. INTRODUCTION .............................................................................................................................. 2
2. DS21Q44 PIN DESCRIPTION ......................................................................................................... 7
3. DS21Q44 PIN FUNCTION DESCRIPTION ................................................................................ 13
4. DS21Q44 REGISTER MAP............................................................................................................. 20
5. PARALLEL PORT........................................................................................................................... 24
6. CONTROL, ID AND TEST REGISTERS ..................................................................................... 24
7. STATUS AND INFORMATION REGISTERS............................................................................. 34
8. ERROR COUNT REGISTERS....................................................................................................... 40
9. DS0 MONITORING FUNCTION................................................................................................... 43
10. SIGNALING OPERATION ............................................................................................................ 45
10.1 PROCESSOR BASED SIGNALING........................................................................................ 45
10.2 HARDWARE BASED SIGNALING........................................................................................ 48
11. PER–CHANNEL CODE GENERATION AND LOOPBACK ................................................... 49
11.1 TRANSMIT SIDE CODE GENERATION............................................................................... 49
11.1.1 Simple Idle Code Insertion and Per-Channel Loopback................................................... 49
11.1.2 Per-Channel Code Insertion .............................................................................................. 50
11.2 RECEIVE SIDE CODE GENERATION .................................................................................. 51
12. CLOCK BLOCKING REGISTERS ............................................................................................... 52
13. ELASTIC STORES OPERATION ................................................................................................ 53
13.1 RECEIVE SIDE......................................................................................................................... 54
13.2 TRANSMIT SIDE ..................................................................................................................... 54
14. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .................................... 54
14.1 HARDWARE SCHEME ........................................................................................................... 54
14.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME ..................................... 55
14.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME ............................... 57
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DS21Q44
15. HDLC CONTROLLER FOR THE SA BITS OR DS0 ................................................................. 59
15.1
15.2
15.3
15.4
GENERAL OVERVIEW........................................................................................................... 59
HDLC STATUS REGISTERS .................................................................................................. 60
BASIC OPERATION DETAILS............................................................................................... 61
HDLC REGISTER DESCRIPTION.......................................................................................... 62
16. INTERLEAVED PCM BUS OPERATION ................................................................................... 69
17. JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .......................... 72
17.1
17.2
17.3
17.4
DESCRIPTION.......................................................................................................................... 72
TAP CONTROLLER STATE MACHINE................................................................................ 73
INSTRUCTION REGISTER AND INSTRUCTIONS ............................................................. 75
TEST REGISTERS.................................................................................................................... 77
18. TIMING DIAGRAMS...................................................................................................................... 82
19. OPERATING PARAMETERS ...................................................................................................... 92
20. 128-PIN TQFP PACKAGE SPECIFICATIONS ........................................................................ 105
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