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DALLAS
SEMICONDUCTOR
PRELIMINARY
3.3V DS21354 and 5V DS21554
E1 Single Chip Transceivers (SCT)
PRELIMINARY
FEATURES
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Complete E1 (CEPT) PCM-30/ISDN-PRI
transceiver functionality
Onboard long and short haul line interface
for clock/data recovery and waveshaping
32-bit or 128-bit crystal-less jitter attenuator
Frames to FAS, CAS, CCS, and CRC4
formats
Integral HDLC controller with 64-byte
buffers configurable for Sa Bits, DS0 or sub
DS0 operation
Dual two–frame elastic store slip buffers
that can connect to asynchronous
backplanes up to 8.192 MHz
Interleaving PCM Bus Operation
8–bit parallel control port that can be used
directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)
Extracts and inserts CAS signaling
Detects and generates remote and AIS
alarms
Programmable output clocks for Fractional
E1, H0, and H12 applications
Fully independent transmit and receive
functionality
Full access to Si and Sa bits aligned with
CRC-4 multiframe
Four separate loopback functions for testing
functions
Large counters for bipolar and code
violations, CRC4 code word errors, FAS
word errors, and E bits
IEEE 1149.1 JTAG-Boundary Scan
Architecture
Pin compatible with DS2154/52/352/552
SCTs
3.3V (DS21354) or 5V (DS21554) supply;
low power CMOS
100–pin LQFP package (14mm X 14mm)
100
1
ORDERING INFORMATION
DS21354L
DS21354LN
DS21554L
DS21554LN
(0
0
C to 70
0
C)
(-40
0
C to +85
0
C)
(0
0
C to 70
0
C)
(-40
0
C to +85
0
C)
DESCRIPTION
The DS21354/554 Single–Chip Transceiver (SCT) contains all of the necessary functions for connection
to E1 lines. The device is an upward compatible version of the DS2153 and DS2154 SCTs. The onboard
clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The
DS21354/554 automatically adjusts to E1 22AWG (0.6 mm) twisted–pair cables from 0 to over 2km in
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12799
Preliminary
DS21354 & DS21554
length. The device can generate the necessary G.703 waveshapes for both 75 ohm coax and 120 ohm
twisted cables. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in
either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and
monitors the data stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa
bit information. The onboard HDLC controller can be used for Sa bit links or DS0s. The device contains
a set of internal registers which the user can access and control the operation of the unit. Quick access via
the parallel control port allows a single controller to handle many E1 lines. The device fully meets all of
the latest E1 specifications including ITU-T G.703,G.704, G.706, G.823, G.932, and I.431, ETS 300 011,
300 233, and 300 166, as well as CTR12 and CTR4.
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Preliminary
TABLE OF CONTENTS
1.
DS21354 & DS21554
INTRODUCTION ...........................................................................................................................5
1.1
1.2
F
UNCTIONAL
D
ESCRIPTION
..........................................................................................................6
DOCUMENT REVISION HISTORY.........................................................................................7
2.
PIN DESCRIPTION ........................................................................................................................9
2.1
PIN FUNCTION DESCRIPTION ............................................................................................14
2.1.1
Transmit Side Pins
..........................................................................................................14
2.1.2
Receive Side Pins
............................................................................................................16
2.1.3
Parallel Control Port Pins
...............................................................................................19
2.1.4
JTAG Test Access Port Pins............................................................................................20
2.1.5
Interleave Bus Operation Pins.........................................................................................21
2.1.6
Line Interface Pins..........................................................................................................21
2.1.7
Supply Pins......................................................................................................................22
3.
PARALLEL PORT........................................................................................................................23
3.1
REGISTER MAP.....................................................................................................................23
4.
CONTROL, ID, AND TEST REGISTERS...................................................................................28
4.1
4.2
4.3
4.4
4.5
P
OWER
–U
P
S
EQUENCE
..............................................................................................................28
F
RAMER
L
OOPBACK
..................................................................................................................33
A
UTOMATIC
A
LARM
G
ENERATION
.............................................................................................33
R
EMOTE
L
OOPBACK
..................................................................................................................35
L
OCAL
L
OOPBACK
.....................................................................................................................35
5.
STATUS AND INFORMATION REGISTERS............................................................................38
5.1
CRC4 S
YNC
C
OUNTER
..............................................................................................................39
6.
ERROR COUNT REGISTERS.....................................................................................................43
6.1
6.2
6.3
6.4
BPV
OR
C
ODE
V
IOLATION
C
OUNTER
.........................................................................................43
CRC4 E
RROR
C
OUNTER
............................................................................................................43
E–B
IT
C
OUNTER
.......................................................................................................................44
FAS E
RROR
C
OUNTER
..............................................................................................................44
7.
8.
DS0 MONITORING FUNCTION.................................................................................................46
SIGNALING OPERATION ..........................................................................................................48
8.1
P
ROCESSOR
B
ASED
S
IGNALING
..................................................................................................48
8.2
H
ARDWARE
B
ASED
S
IGNALING
..................................................................................................50
8.2.1
Receive Side
....................................................................................................................50
8.2.2
Transmit Side
..................................................................................................................50
9.
PER–CHANNEL CODE GENERATION AND LOOPBACK ....................................................52
9.1
T
RANSMIT
S
IDE
C
ODE
G
ENERATION
..........................................................................................52
9.1.1
Simple Idle Code Insertion and Per–Channel Loopback.................................................52
9.1.2
Per–Channel Code Insertion
...........................................................................................53
9.2
R
ECEIVE
S
IDE
C
ODE
G
ENERATION
.............................................................................................53
10.
11.
CLOCK BLOCKING REGISTERS .........................................................................................55
ELASTIC STORES OPERATION ...........................................................................................57
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Preliminary
11.1
11.2
12.
12.1
12.2
12.3
13.
DS21354 & DS21554
R
ECEIVE
S
IDE
...........................................................................................................................57
T
RANSMIT
S
IDE
........................................................................................................................57
ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION..................................58
H
ARDWARE
S
CHEME
.................................................................................................................58
I
NTERNAL
R
EGISTER
S
CHEME
B
ASED
O
N
D
OUBLE
–F
RAME
..........................................................58
I
NTERNAL
R
EGISTER
S
CHEME
B
ASED
O
N
CRC4 M
ULTIFRAME
....................................................60
HDLC CONTROLLER FOR THE SA BITS OR DS0.............................................................62
13.1 G
ENERAL
O
VERVIEW
.................................................................................................................62
13.2 HDLC S
TATUS
R
EGISTERS
........................................................................................................62
13.3 B
ASIC
O
PERATION
D
ETAILS
.......................................................................................................63
13.3.1 Receive a HDLC Message
...............................................................................................63
13.3.2 Transmit an HDLC Message...........................................................................................63
13.4 HDLC R
EGISTER
D
ESCRIPTION
.................................................................................................64
14.
14.1
14.2
14.3
15.
15.1
15.2
15.3
16.
16.1
16.2
17.
17.1
17.2
18.
19.
19.1
19.2
19.3
19.4
20.
LINE INTERFACE FUNCTIONS ............................................................................................70
R
ECEIVE
C
LOCK
A
ND
D
ATA
R
ECOVERY
.....................................................................................70
T
RANSMIT
W
AVESHAPING
A
ND
L
INE
D
RIVING
...........................................................................71
J
ITTER
A
TTENUATOR
................................................................................................................72
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT........................76
D
ESCRIPTION
............................................................................................................................76
I
NSTRUCTION
R
EGISTER
............................................................................................................79
T
EST
R
EGISTERS
.......................................................................................................................81
INTERLEAVED PCM BUS OPERATION ..............................................................................85
C
HANNEL
I
NTERLEAVE
..............................................................................................................86
F
RAME
I
NTERLEAVE
..................................................................................................................86
FUNCTIONAL TIMING DIAGRAMS.....................................................................................87
R
ECEIVE
...................................................................................................................................87
T
RANSMIT
................................................................................................................................90
OPERATING PARAMETERS .................................................................................................96
AC TIMING PARAMETERS AND DIAGRAMS....................................................................97
M
ULTIPLEXED
B
US
AC C
HARACTERISTICS
.................................................................................97
N
ON
-M
ULTIPLEXED
B
US
AC C
HARACTERISTICS
......................................................................100
R
ECEIVE
S
IDE
AC C
HARACTERISTICS
......................................................................................103
T
RANSMIT
AC C
HARACTERISTICS
...........................................................................................106
MECHANICAL DESCRIPTION............................................................................................109
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Preliminary
DS21354 & DS21554
1. INTRODUCTION
The DS21354/554 is a superset version of the popular DS2153 and DS2154 SCTs offering the new
features listed below. All of the original features of the DS2153 and DS2154 have been retained and
software created for the original devices is transferrable into the DS21354/554.
New Features in the DS21354 and DS21554
FEATURE
HDLC controller with 64-byte buffers for Sa bits or DS0s or sub DS0s
Interleaving PCM bus operation
IEEE 1149.1 JTAG-Boundary Scan Architecture
3.3V (DS21354 only) supply
Line Interface Support for the G.703 2.048 Synchronization Interface
Customer Disconnect Indication (...101010...) Generator
Open Drain Line Driver Option
SECTION
15
18
17
2 and 3
16
6
16
New Features in the DS2154 (also in the DS21354 and DS21554)
FEATURE
Option for non–multiplexed bus operation
Crystal–less jitter attenuation
Additional hardware signaling capability including:
Receive signaling reinsertion to a backplane multiframe sync
Availability of signaling in a separate PCM data stream
Signaling freezing Interrupt generated on change of signaling data
Improved receive sensitivity: 0 dB to –43 dB
Per–channel code insertion in both transmit and receive paths
Expanded access to Sa and Si bits
RCL, RLOS, RRA, and RAIS alarms now interrupt on change of state
8.192 MHz clock synthesizer
Per–channel loopback
Addition of hardware pins to indicate carrier loss and signaling freeze
Line interface function can be completely decoupled from the framer/formatter to allow:
Interface to optical, HDSL, and other NRZ interfaces
“tap” the transmit and receive bipolar data streams for monitoring purposes
Be able to corrupt data and insert framing errors, CRC errors, etc.
Transmit and receive elastic stores now have independent backplane clocks
Ability to monitor one DS0 channel in both the transmit and receive paths
Access to the data streams in between the framer/formatter and the elastic stores
AIS generation in the line interface that is independent of loopbacks
Transmit current limiter to meet the 50 mA short circuit requirement
Option to extend carrier loss criteria to a 1 ms period as per ETS 300 233
Automatic RAI generation to ETS 300 011 specifications
SECTION
1 and 2
12
7
12
8
11
4
1
8
1
1
1
6
1
1 and 3
12
3
3
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