ks0108b.pdf

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KS0108B
INTRODUCTION
64
CH SEGMENT DRIVER FOR DOT MATRIX LCD
100 QFP
The KS0108B is a LCD driver LSl with 64 channel output
for dot matrix liquid crystal graphic display system. This
device consists of the display RAM, 64 bit data latch 64 bit
drivers and decoder logics. It has the internal display RAM
for storing the display data transferred from a 8 bit micro
controller and generates the dot matrix Iiquid crystal driv-
ing signals corresponding to stored data.The KS0108B
composed of the liquid crystal display system in combina-
tion with the KS0107B (64 common driver)
FEATURES
•
Dot matrix LCD segment driver with 64 channel output
•
Input and Output signal
- Input: 8 bit parallel display data
Control signal from MPU
Splitted bias voltage (V1R, V1L, V2R, V2L,
V3R. V3L, V4R, V4L)
- Output: 64 channel waveform for LCD driving.
•
Display data is stored in display data RAM from MPU.
•
Interface RAM
- Capacity: 512 bytes (4096 bits)
- RAM bit data: RAM bit data = 1:ON
RAM bit data- = 0:OFF
•
Applicable LCD duty: 1/32~1/64
•
LCD driving voltage: 8V~17V(V -V
EE
)
DD
•
Power supply voltage: + 5V
±10%
Driver
COMMON
KS0107B
SEGMENT
Other KS0108B
Controller
MPU
•
High voltage CMOS process.
•
100QFP and bare chip available.
KS0108B
BLOCK DIAGRAM
64
CH SEGMENT DRIVER FOR DOT MATRIX LCD
DB<0:7>
CLK1 CLK2
CS1B
CS2B
INPUT REGISTER
OUTPUT REGISTER
CS3
I/O
BUFFER
R/W
RS
E
8
8
RSTB
DISPLAY
ON/OFF
1
BUSY
INSTRUCTION
DECODER
6
3
Y-COUNTER
6
X-DECODER
Y-DECODER
6
64
DISPLAY START LINE REGISTER
8
ADC
CL
PAGE SELECTOR
Z DECODER
6
64
DISPLAY DATA RAM
512¡¿8=4096 bits
8
FRM
64
DATA LATCH
64
V0L
V2L
V3L
V5L
M
LCD DRIVER
V0R
V2R
V3R
V5R
S64
S63
S2
S1
64
CH SEGMENT DRIVER FOR DOT MATRIX LCD
Fig.2. 100QFP Top
V
EE1
DB1
DB0
V3L
V2L
V5L
V0L
S10
S11
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DB2 81
DB3 82
DB4 83
DB5 84
DB6 85
DB7 86
NC
NC
NC
CS3 90
CS2B
91
92
93
CS1B
RSTB
R/W 94
RS
CL
CLK2 97
CLK1 98
E
99
96
95
89
88
87
S22
V
SS
S1
S2
S3
S4
S5
S6
S7
S8
S9
50
49
48
47
46
45
44
43
42
41
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
KS0108B
40
39
38
37
36
35
34
33
32
31
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
KS0108B
FRM 100
1
ADC
2
M
3
V
DD
4
V3R
5
V2R
6
V5R
7
V0R
8
V
EE2
9
S64
10
S63
11
S62
12
S61
13
S60
14
S59
15
S58
16
S57
17
S56
18
S55
19
S54
20
S53
21
S52
22
S51
23
S50
24
S49
25
S48
26
S47
27
S46
28
S45
29
S44
30
S43
View
KS0108B
64
CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCIPTION
PIN (NO)
3
78
73, 8
SYMBOL
V
DD
V
SS
V
EE1.2
INPUT/OUTPUT
DESCRIPTION
Power
For internal logic circuit (+5V±10%)
GND (0V)
For LCD driver circuit
V
SS
=0V, V
DD
=5V
¡¾
10% V
DD
-V
EE
=8V~17V
V
EE1
and V
EE2
is connected by the same voltage.
Power
Bias supply voltage terminals to drive the LCD.
Select Level
V0L(R), V5L(R)
Input
Non-Select Level
V2L(R), V3L(R)
74, 7
76, 5
77, 4
75, 6
92
91
90
2
1
V0L, V0R
V2L, V2R
V3L, V3R
V5L, V5R
CS1B
CS2B
CS3
M
ADC
Input
Input
100
FRM
Input
99
E
Input
98
97
96
CLK1
CLK2
CL
Input
Input
95
RS
Input
94
R/W
Input
79~86
DB0~DB7
Input/Output
Chip selection
In order to interface data for input or output
The terminals have to be CS1B=L, CS2B=L, and CS3=H.
Alternating signal input for LCD driving.
Address control signal of Y address counter.
ADC=H→DB<0:7>=0→Y0→S1
DB<0:7>=63→Y63→S64
ADC=L→DB<0:7>=0→Y63→S64
DB<0:7>=63→Y0→S1
Synchronous control signal.
Presets the 6-bit Z counter and syncronizes the common signal with the
frame signal when the frame signal becomes high.
Enable signal.
write mode (R/W=L)
→
data of DB<0:7> is latched at
the falling edge of E.
read mode (R/W=H)
→
DB<0:7> appears the reading
data while E is at high level.
2 phase clock signal for internal operation.
Used to execute operations for input/output of display
RAM data and others.
Display synchronous signal.
Display data is latched at rising time of the CL signal and increments the
Z-address counter at the CL falling time.
Data or Instruction.
RS=H→DB<0:7> : Display RAM Data
RS=L→DB<0:7> : Instruction Data
Read or Write.
R/W=H
→
Data appears at DB<0:7> and can be read
by the CPU while E=H, CS1B=L, CS2B=L
and CS3=H.
R/W=L
¡æ
Display data DB<0:7> can be written at falling of E
when CS1B=L, CS2B=L and CS3=H.
Data bus.
There state I/O common terminal.
KS0108B
64
CH SEGMENT DRIVER FOR DOT MATRIX LCD
PIN DESCRIPTION
(continued)
PIN (NO)
72~9
NAME
S1~S64
INPUT/OUTPUT
DESCRIPTION
Output
LCD Segment driver output.
Display RAM data 1:ON
Display RAM data 0:OFF
(Relation of display RAM data & M)
M
L
H
93
RSTB
Input
DATA
L
H
L
H
Output Level
V
2
V
0
V
3
V
5
87~89
NC
Reset signal.
When RSTB=L,
(1) ON/OFF register becomes set by 0. (display off)
(2) Display start line register becomes set by 0
(Z-address 0 set, display from line 0)
After releasing reset, this condition can be changed only by instruction.
No connection.(open)
MAXIMUM ABSOLUTE LIMIT
Characteristic
Operating Voltage
Supply Voltage
Driver Supply Voltage
Symbol
V
DD
V
EE
V
B
V
LCD
T
OPR
T
STG
Value
-0.3~+7.0
V
DD
-19.0~V
DD
+0.3
-0.3~V
DD
+0.3
V
EE
-0.3~V
DD
+0.3
-30~+85
-55~+125
Unit
V
V
V
V
°
C
°
C
Note
*1
*4
*1,3
*2
Operating Temperature
Storage Temperature
*1. Based on V
SS
=0V.
*2. Applies the same supply voltage to V and V
EE2
. V
LCD
=V
DD
-V
EE
.
EE1
*3. Applies to M, FRM, CL, RSTB, ADC, CLK1, CLK2, CS1B, CS2B, CS3, E, R/W, RS and DB0~DB7.
*4. Applies V0L(R), V2L(R), V3L(R) and V5L(R).
Voltage level: V
DD
≥V0L=VOR≥V2L=V2R≥V3L=V3R≥V5L=V5R≥V
EE
.

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