dsp56362 datasheet.pdf

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MOTOROLA
SEMICONDUCTOR ADVANCE INFORMATION
Order this document by:
DSP56362/D
Rev 2.1, 11/00
Advance Information
DSP56362
24-Bit Audio DIgital Signal Processor
Motorola designed the DSP56362 to support digital audio applications requiring digital audio
compression and decompression, sound field processing, acoustic equalization, and other digital
audio algorithms. The DSP56362 uses the high performance, single-clock-per-cycle DSP56300
core family of programmable CMOS digital signal processors (DSPs) combined with the audio
signal processing capability of the Motorola Symphony™ DSP family, as shown in
Figure 1.
This
design provides a two-fold performance increase over Motorola’s popular Symphony family of
DSPs while retaining code compatibility. Significant architectural enhancements include a barrel
shifter, 24-bit addressing, instruction cache, and direct memory access (DMA). The DSP56362
offers 100 million instructions per second (MIPS) using an internal 100 MHz clock at 3.3 V.
2
16
12
5
Program RAM/
X Data
Instruction
RAM
Y Data
Cache
5632
×
24
RAM
3072
×
24
5632
×
24
ROM
Program ROM
6144
×
24
ROM
30K
×
24
6144
×
24
Bootstrap ROM
192
×
24
Triple
Timer
DAX
(SPDIF)
Host
Interface
ESAI
SHI
Memory
Expansion
Area
PIO_EB
PM_EB
XM_EB
Address
Generation
Unit
Six Channel
DMA Unit
YAB
XAB
PAB
DAB
YM_EB
Peripheral
Expansion Area
External
Address
Bus
Switch
DRAM/SRAM
Bus
Interface
&
I - Cache
Control
18
Address
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
11
Control
Internal
Data
Bus
External
Data Bus
Switch
24
Data
EXTAL
Clock
Generator
PLL
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
CLKOUT
Data ALU
24
×
24 + 56
→
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Power
Mngmnt.
6
JTAG
OnCE
RESET
PINIT/NMI
AA0456G
Figure 1 DSP56362 Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© 1999, 2000, MOTOROLA, INC.
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1
IBIS MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INDEX-I
FOR TECHNICAL ASSISTANCE:
Telephone:
Email:
Internet:
1-800-521-6274
dsphelp@dsp.sps.mot.com
http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
“deasserted”
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET
pin is active when low.)
Means that a high true (active high) signal is high or that a low true (active low)
signal is low
Means that a high true (active high) signal is low or that a low true (active low)
signal is high
Signal/Symbol
PIN
PIN
PIN
PIN
Note:
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage*
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
*Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
!!
DSP56362 Advance Information
MOTOROLA
DSP56362
Features
FEATURES
•
Multimode, multichannel decoder software functionality
– Dolby Digital and Pro Logic
– MPEG2 5.1
– DTS
– Bass management
Digital audio post-processing capabilities
– 3D Virtual surround sound
– Lucasfilm THX5.1
– Soundfield processing
– Equalization
Digital Signal Processing Core
– 100 MIPS with a 100 MHz clock at 3.3 V +/- 5%
– Object code compatible with the DSP56000 core
– Highly parallel instruction set
– Data arithmetic logic unit (ALU)
• Fully pipelined 24 x 24-bit parallel multiplier-accumulator (MAC)
•
•
•
–
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and
parsing)
Conditional ALU instructions
24-bit or 16-bit arithmetic support under software control
•
•
Program control unit (PCU)
• Position independent code (PIC) support
•
•
•
•
•
Addressing modes optimized for DSP applications (including immediate offsets)
On-chip instruction cache controller
On-chip memory-expandable hardware stack
Nested hardware DO loops
Fast auto-return interrupts
–
Direct memory access (DMA)
• Six DMA channels supporting internal and external accesses
•
•
•
One-, two-, and three- dimensional transfers (including circular buffering)
End-of-block-transfer interrupts
Triggering from interrupt lines and all peripherals
–
Phase-locked loop (PLL)
• Software programmable PLL-based frequency synthesizer for the core clock
•
•
Allows change of low-power divide factor (DF) without loss of lock
Output clock with skew elimination
MOTOROLA
DSP56362 Advance Information
iii
DSP56362
Features
–
Hardware debugging support
• On-Chip Emulation (OnCE‘) module
•
•
Joint Action Test Group (JTAG) test access port (TAP)
Address trace mode reflects internal program RAM accesses at the external port
•
On-Chip Memories
– Modified Harvard architecture allows simultaneous access to program and data
memories
– 30720 x 24-bit on-chip program ROM
1
(disabled in 16-bit compatibility mode)
– 6144 x 24-bit on-chip X-data ROM
1
– 6144 x 24-bit on-chip Y-data ROM
1
– Program RAM, instruction cache, X data RAM, and Y data RAM sizes are
programmable.
Instruction
Cache
Disabled
Enabled
Disabled
Enabled
Switch
Mode
Disabled
Disabled
Enabled
Enabled
Program RAM
Size
3072
×
24-bit
2048
×
24-bit
5120
×
24-bit
4096
×
24-bit
Instruction
Cache Size
0
1024
×
24-bit
0
1024
×
24-bit
X Data RAM
Size
5632
×
24-bit
5632
×
24-bit
5632
×
24-bit
5632
×
24-bit
Y Data RAM
Size
5632
×
24-bit
5632
×
24-bit
3584
×
24-bit
3584
×
24-bit
•
•
– 192 x 24-bit bootstrap ROM (disabled in sixteen-bit compatibility mode)
Off-Chip Memory Expansion
– Data memory expansion to 256K x 24-bit word memory for P, X, and Y memory using
SRAM.
– Data memory expansion to 16M x 24-bit word memory for P, X, and Y memory using
DRAM.
– External memory expansion port( twenty-four data pins for high speed external
memory access allowing for a large number of external accesses per sample)
– Chip select logic for glueless interface to SRAMs
– On-chip DRAM controller for glueless interface to DRAMs
Peripheral and Support Circuits
– Enhanced serial audio interface (ESAI) includes:
• Six serial data lines, 4 selectable as receive or transmit and 2 transmit only.
•
•
–
Master or slave capability
I
2
S, Sony, AC97, and other audio protocol implementations
Serial host interface (SHI) features:
• SPI protocol with multi-master capability
•
•
I
2
C protocol with single-master capability
Ten-word receive FIFO
1.These ROMs may be factory programmed with data or programs provided by the application de-
veloper.
iv
DSP56362 Advance Information
MOTOROLA
DSP56362
Documentation
•
–
–
Support for 8-, 16-, and 24-bit words.
•
Byte-wide parallel host interface (HDI08) with DMA support
DAX features one serial transmitter capable of supporting S/PDIF, IEC958, IEC1937,
CP-340, and AES/EBU digital audio formats; alternate configuration supports up to
two GPIO lines
– Triple timer module with single external interface or GPIO line
– On-chip peripheral registers are memory mapped in data memory space
Reduced Power Dissipation
– Very low-power (3.3 V) CMOS design
– Wait and stop low-power standby modes
– Fully-static logic, operation frequency down to 0 Hz (dc)
– Optimized power management circuitry (instruction-dependent, peripheral-
dependent, and mode-dependent)
Package
•
144-pin plastic thin quad flat pack (TQFP) surface-mount package
DOCUMENTATION
Table 1
lists the documents that provide a complete description of the DSP56362 and are
required to design properly with the part. Documentation is available from a local Motorola
distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or
through the Motorola DSP home page on the Internet (the source for the latest information).
Table 1
Document Name
DSP56300 Family Manual
DSP56362 Documentation
Description
Order Number
DSP56300FM/AD
Detailed description of the 56000-family
architecture and the 24-bit core processor and
instruction set
Detailed description of memory, peripherals,
and interfaces
Electrical and timing specifications; pin and
package descriptions
DSP56362 User’s Manual
DSP56362 Advance
Information
DSP56362UM/AD
DSP56362/D
There is also a product brief for this chip.
DSP56362 Product Brief
Brief description of the chip
DSP56362P/D
MOTOROLA
DSP56362 Advance Information
v

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