//****************************************************************************** // Set up one-time programming for BB ASIC //****************************************************************************** // Address Value // Comments // ======= ====== == ======== WRITE INITONLY 0xe540 0x0020 // AMCR (Audio Module Control Register) -- Enabled VBEN DELAY INITONLY 0x7fff // need extra delay for ML2022 DSP WRITE INITONLY 0xe540 0x0000 // AMCR -- Disable VBEN DELAY INITONLY 0x7fff // Configure serial bus: WRITE INITONLY 0xe570 0xfdfd // FQCR 24 bits, MSB first, CLK 26 MHz WRITE INITONLY 0xef40 0x0000 // FCH0R select data channel WRITE INITONLY 0xef41 0x0000 // FCH1R WRITE INITONLY 0xef42 0x0000 // FCH2R WRITE INITONLY 0xef43 0x0000 // FCH3R WRITE INITONLY 0xef44 0x0000 // FCH4R WRITE INITONLY 0xef45 0x0000 // FCH0R select data channel WRITE INITONLY 0xef46 0x0000 // FCH1R WRITE INITONLY 0xef47 0x0000 // FCH2R WRITE INITONLY 0xef48 0x0000 // FCH3R WRITE INITONLY 0xef49 0x0000 // FCH4R WRITE INITONLY 0xef4a 0x0000 // FCH0R select data channel WRITE INITONLY 0xef4b 0x0000 // FCH1R WRITE INITONLY 0xef4c 0x0000 // FCH2R WRITE INITONLY 0xef4d 0x0000 // FCH3R WRITE INITONLY 0xef4e 0x0000 // FCH4R WRITE INITONLY 0xef4f 0x0000 // FCH0R select data channel WRITE INITONLY 0xef50 0x0000 // FCH1R WRITE INITONLY 0xef51 0x0000 // FCH2R WRITE INITONLY 0xef52 0x0000 // FCH3R WRITE INITONLY 0xef53 0x0000 // FCH4R WRITE ANYBAND 0xe57e 0x0000 // GPWR WRITE INITONLY 0xe001 0x1080 // SCR - digRF WRITE INITONLY 0xe5a0 0x8000 // bit0: 0-stream mode; 1-blk mode. DRFMODE Start with digRF stream mode WRITE INITONLY 0xe5a1 0x2020 // DRFLPM preamble and posamble - in digRF bits WRITE INITONLY 0xe5a2 0x0000 // DRFPREH WRITE INITONLY 0xe5a3 0x0000 // DRFPREL WRITE INITONLY 0xe5a4 0x0000 // DRFPOSH WRITE INITONLY 0xe5a5 0x0000 // DRFPOSL #if (RF_CHIP_REVISION >= 20) #include "init_bcm2091b0.txt" #elif (RF_CHIP_REVISION == 11) #include "init_bcm2091a1.txt" #else #include "init_bcm2091a0.txt" #endif RF_WRITE_SEND INITONLY RF_CDAC_WRITE INITONLY 0x09c8 0x1c00 //B0 same as A1 for coarse RF_WRITE_SEND INITONLY // Set up programming for BB ASIC. // Address Value // Comments // ======= ====== == ======== WRITE ANYBAND 0xe546 0x0002 // AMPCR WRITE ANYBAND 0xe5c0 0x0000 // RCOR WRITE ANYBAND 0xe5c1 0x0000 // RCDR #if (RF_CHIP_REVISION < 20) WRITE ANYBAND 0xe5c2 0x0037 // RSDR #else WRITE ANYBAND 0xe5c2 0x003c //0x0037// 0x0033 // RSDR #endif WRITE ANYBAND 0xe501 0x1387 // CHAR (Counter Hold A Register) WRITE ANYBAND 0xe502 0x1387 // CHBR (Counter Hold B Register) WRITE ANYBAND 0xe573 0x8000 // FRQOR (Frequency Offset DAC Register) - Enable PDEN //???not in RDB??? WRITE ANYBAND 0xe582 0x0000 // TCDR +++ WRITE ANYBAND 0xe587 0x0000 // MFCR WRITE ANYBAND 0xe581 0x0000 // TCOR #if (RF_CHIP_REVISION >= 20) #if defined(_RHEA2091_) WRITE ANYBAND 0xe584 0x003a // TSDR #elif (defined(THUNDERBIRD)&&(THUNDERBIRD_BOARD_REV>=41)) WRITE ANYBAND 0xe584 0x0036 // TSDR #else WRITE ANYBAND 0xe584 0x0037 // TSDR #endif #else WRITE ANYBAND 0xe584 0x003a // TSDR #endif WRITE ANYBAND 0xe58b 0x00cf // TRDR[0] WRITE ANYBAND 0xe58c 0x8365 // TRDR[1] WRITE ANYBAND 0xe58d 0x85c3 // TRDR[2] WRITE ANYBAND 0xe58e 0x8833 // TRDR[3] WRITE ANYBAND 0xe58f 0x8aa3 // TRDR[4] WRITE ANYBAND 0xe5c6 0x1111 // MPGR (Multislot Programmable Gain Reg) WRITE ANYBAND 0xe5c7 0x0000 // PGDR (Programmable Gain Delay Register) #if (defined(MULTI_BOM) && defined(BOM2)) WRITE ANYBAND 0xe51f 0x000d // GPWSR - Latch from WCDMA #else WRITE ANYBAND 0xe51f 0x000f // GPWSR - Latch from WCDMA #endif //***************************************************************************** //Setup RX LPF filter //***************************************************************************** // Address Value // Comments // ======= ====== == ======== WRITE INITONLY 0xe5c3 0x0000 //PHINC WRITE INITONLY 0xe5c8 0x0000 //REC4ADR WRITE INITONLY 0xe5c9 0x0000 //REC4DAT WRITE INITONLY 0xe5c9 0x0000 WRITE INITONLY 0xe5c9 0x0000 WRITE INITONLY 0xe5c9 0x0000 WRITE INITONLY 0xe5c9 0x1FFE WRITE INITONLY 0xe5c9 0x0004 WRITE INITONLY 0xe5c9 0x0012 WRITE INITONLY 0xe5c9 0x1FF2 WRITE INITONLY 0xe5c9 0x1FAC WRITE INITONLY 0xe5c9 0x0007 WRITE INITONLY 0xe5c9 0x00FC WRITE INITONLY 0xe5c9 0x0057 WRITE INITONLY 0xe5c9 0x1D9E WRITE INITONLY 0xe5c9 0x1E1F WRITE INITONLY 0xe5c9 0x0651 WRITE INITONLY 0xe5c9 0x0FF1 WRITE INITONLY 0xe5ca 0x0000 //REC3ADR WRITE INITONLY 0xe5cb 0x0000 //REC3DAT WRITE INITONLY 0xe5cb 0x0000 WRITE INITONLY 0xe5cb 0x0000 WRITE INITONLY 0xe5cb 0x0ffe WRITE INITONLY 0xe5cb 0x0ffd WRITE INITONLY 0xe5cb 0x0007 WRITE INITONLY 0xe5cb 0x0010 WRITE INITONLY 0xe5cb 0x0ff2 WRITE INITONLY 0xe5cb 0x0fca WRITE INITONLY 0xe5cb 0x000d WRITE INITONLY 0xe5cb 0x0090 WRITE INITONLY 0xe5cb 0x0020 WRITE INITONLY 0xe5cb 0x0eb8 WRITE INITONLY 0xe5cb 0x0f1c WRITE INITONLY 0xe5cb 0x0346 WRITE INITONLY 0xe5cb 0x07ff #if (defined (RFSPI) || defined (MIPI_ARMCTRL)) #if defined(RHEARAY) WRITE ANYBAND 0xe51b 0x0006 // GPSPI[2:0] enable 2G SPI to GPEN[2:0] #else WRITE ANYBAND 0xe51b 0x0007 // GPSPI[2:0] enable 2G SPI to GPEN[2:0] #endif WRITE ANYBAND 0xe57e 0x0080 //GPWR GPEN7 //WRITE INITONLY 0xe57f 0x0080 //GPSR //WRITE INITONLY 0xe51f 0x0000 //GPWSR #endif
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