/////////////////////////// // 3G INIT /////////////////////////// //Should match 3G restore settings WRITE_3G_INIT 0x0001F000 //WRITE_3G_INIT 0x09114384 //WRITE_3G_INIT 0x0902567c #if defined(_RHEA2091_) WRITE_3G_INIT 0x04c23c91 // hptx_clpc_log_lin_sel=1 WRITE_3G_INIT 0x05150040 // hptx_prePA_lut_ctr = 1, hptx_prePA_lut_addr_byp = 0 #else WRITE_3G_INIT 0x04c23c90 // hptx_clpc_log_lin_sel=1 WRITE_3G_INIT 0x05158040 // hptx_prePA_lut_ctr = 1, hptx_prePA_lut_addr_byp = 0 #endif // _RHEA2091_ WRITE_3G_INIT 0x07130063 // hpreg_clpc_adcBuf_gain = 5 WRITE_3G_INIT 0x0902567f // o_tx_TXLO_LDO_vout = 5, o_tx_Envpwrdn_ovr = 1, force on TXLO_LDO to support Rcal WRITE_3G_INIT 0x090b0800 // o_tx_BBBWQ_ovrVal = 0, o_tx_rout=4 WRITE_3G_INIT 0x090e0810 // o_tx_clpc_dcin_level = 4 WRITE_3G_INIT 0x09112383 // o_tx_CLPC_SDconv_Pole = 0x3, o_tx_CLPC_SDconv_Attn = 0x8 WRITE_3G_INIT 0x0931031e // analog DCOC filter BW WRITE_3G_INIT 0x094408a8 // o_txpll_sdldo = 4, o_txpll_dgldo=3, o_txpll_cpldo=2 WRITE_3G_INIT 0x09500390 // o_txpll_vrangl=3, o_txpll_vrangh=4 and o_txpll_dac=12 WRITE_3G_INIT 0x09c02901 // o_bgr_txdac_mode = 0 (disable PTAT current for DAC). o_bgr_rxbb_vcm_ctrl = 5 WRITE_3G_INIT 0x0c410005 // rx_Cload = 0 for Band VIII & 5 for Band V WRITE_3G_INIT 0x0c420653 // rx_Cload_HB = 6 for Band III, 5 for Band II, & 3 for Band I WRITE_3G_INIT 0x090502b8 // o_tx_PrePaCC=0 WRITE_3G_INIT 0x00000040 #if defined(_RHEA2091_) //WRSSI Settingsanalog related conrols WRITE_3G_INIT 0x09220095 WRITE_3G_INIT 0x09350280 WRITE_3G_INIT 0x09e80002 WRITE_3G_INIT 0x09e92085 WRITE_3G_INIT 0x093f0008 #else #endif //WRSSI buffer gain, ADC and ripple control WRITE_3G_INIT 0x00191c80 WRITE_3G_INIT 0x00221c40 WRITE_3G_INIT 0x02530400 WRITE_3G_INIT 0x02590c01 WRITE_3G_INIT 0x0258f613 ///////////////////////////////////////////////// // 3G band dependent RF reg writes ///////////////////////////////////////////////// //Band IV WRITE_3G_DYN BAND4 0x91000fe // force override TXLO_*_PM to 6 for 3G mode thus bypassing LUT WRITE_3G_DYN BAND4 0x9250000 // un-overwrite o_rx_GC_800 or o_rx_GC_900 WRITE_3G_DYN BAND4 0x965151e // o_rxpll_sdldo=5, o_rxpll_dgldo=4 // Band V WRITE_3G_DYN BAND5 0x91000ef // force override TXLO_*_PM to 6 for 3G mode thus bypassing LUT WRITE_3G_DYN BAND5 0x9250040 // LB2 o_rx_GC_900_ovr & ovrVal WRITE_3G_DYN BAND5 0x965191e // o_rxpll_sdldo=6, o_rxpll_dgldo=4 // Band VIII WRITE_3G_DYN BAND8 0x91000ef // force override TXLO_*_PM to 6 for 3G mode thus bypassing LUT WRITE_3G_DYN BAND8 0x9250040 // LB2 o_rx_GC_900_ovr & ovrVal WRITE_3G_DYN BAND8 0x965191e // o_rxpll_sdldo=6, o_rxpll_dgldo=4 // Band III WRITE_3G_DYN BAND3 0x91000fe // force override TXLO_*_PM to 6 for 3G mode thus bypassing LUT WRITE_3G_DYN BAND3 0x9250000 // un-overwrite o_rx_GC_800 or o_rx_GC_900 WRITE_3G_DYN BAND3 0x965111e // o_rxpll_sdldo=4, o_rxpll_dgldo=4 // Band II WRITE_3G_DYN BAND2 0x91000fe // force override TXLO_*_PM to 6 for 3G mode thus bypassing LUT WRITE_3G_DYN BAND2 0x9250000 // un-overwrite o_rx_GC_800 or o_rx_GC_900 WRITE_3G_DYN BAND2 0x965111e // o_rxpll_sdldo=4, o_rxpll_dgldo=4 //Band I WRITE_3G_DYN BAND1 0x91000fe // force override TXLO_*_PM to 6 for 3G mode thus bypassing LUT WRITE_3G_DYN BAND1 0x9250000 // un-overwrite o_rx_GC_800 or o_rx_GC_900 WRITE_3G_DYN BAND1 0x965151e // o_rxpll_sdldo=5, o_rxpll_dgldo=4 /////////////////////////// // 3G RESTORE /////////////////////////// //Should match 3G INIT settings WRITE_3G_RESTORE 0x0001F000 #if defined(_RHEA2091_) WRITE_3G_RESTORE 0x04c23c91 // hptx_clpc_log_lin_sel=1 WRITE_3G_RESTORE 0x05150040 // hptx_prePA_lut_ctr = 1, hptx_prePA_lut_addr_byp = 0 #else WRITE_3G_RESTORE 0x04c23c90 // hptx_clpc_log_lin_sel=1 WRITE_3G_RESTORE 0x05158000 // hptx_prePA_lut_ctr = 1, hptx_prePA_lut_addr_byp = 0 #endif // _RHEA2091_ WRITE_3G_RESTORE 0x07130063 // hpreg_clpc_adcBuf_gain = 5 WRITE_3G_RESTORE 0x0902567f // o_tx_TXLO_LDO_vout = 5, o_tx_Envpwrdn_ovr = 1, force on TXLO_LDO to support Rcal WRITE_3G_RESTORE 0x090b0800 // o_tx_BBBWQ_ovrVal = 0, o_tx_rout=4 WRITE_3G_RESTORE 0x090e0810 // o_tx_clpc_dcin_level = 4 WRITE_3G_RESTORE 0x09112383 // o_tx_CLPC_SDconv_Pole = 0x3, o_tx_CLPC_SDconv_Attn = 0x8 WRITE_3G_RESTORE 0x0931031e // analog DCOC filter BW WRITE_3G_RESTORE 0x094408a8 // o_txpll_sdldo = 4, o_txpll_dgldo=3, o_txpll_cpldo=2 WRITE_3G_RESTORE 0x09500390 // o_txpll_vrangl=3, o_txpll_vrangh=4 and o_txpll_dac=12 WRITE_3G_RESTORE 0x09c02901 // o_bgr_txdac_mode = 0 (disable PTAT current for DAC). o_bgr_rxbb_vcm_ctrl = 5 WRITE_3G_RESTORE 0x0c410005 // rx_Cload = 0 for Band VIII & 5 for Band V WRITE_3G_RESTORE 0x0c420653 // rx_Cload_HB = 6 for Band III, 5 for Band II, & 3 for Band I WRITE_3G_RESTORE 0x090502b8 // o_tx_PrePaCC=0 WRITE_3G_RESTORE 0x00000040 //write to bit 6 to soft reset TX PLL sigma delta to clear 3G TX frequency offset -- required when returning from 2G Tx. //////////////////////////// // 2G RESTORE (900) /////////////////////////// //Should be duplicated in 2G INIT WRITE_2G_RESTORE 0x00aa3fff WRITE_2G_RESTORE 0x00ab3fff WRITE_2G_RESTORE 0x0931041e // analog DCOC filter BW WRITE_2G_RESTORE 0x00013000 WRITE_2G_RESTORE 0x09114383 //DVT Parm Static #if defined(_RHEA2091_) WRITE_2G_RESTORE 0x04c23c91 // hptx_clpc_log_lin_sel=1 #else WRITE_2G_RESTORE 0x04c23c90 // hptx_clpc_log_lin_sel=1 #endif // _RHEA2091_ #if defined(_RHEA2091_) WRITE_2G_RESTORE 0x05158040 //hptx_prePA_lut_ctrl = 1,hptx_prePA_lut_addr_offset_sel=1 #else WRITE_2G_RESTORE 0x05158000 //hptx_prePA_lut_ctrl = 1,hptx_prePA_lut_addr_offset_sel=1 #endif // _RHEA2091_ WRITE_2G_RESTORE 0x07130064 // hpreg_clpc_adcBuf_gain = 4 WRITE_2G_RESTORE 0x090e0410 // o_tx_clpc_dcin_level = 1 WRITE_2G_RESTORE 0x09112388 // o_tx_CLPC_SDconv_Pole = 0x8, o_tx_CLPC_SDconv_Attn = 0x8 WRITE_2G_RESTORE 0x09c06901 // o_bgr_txdac_mode = 1 (enable PTAT current for DAC). o_bgr_rxbb_vcm_ctrl = 5 WRITE_2G_RESTORE 0x0c410005 // rx_Cload = 0 for Band VIII & 5 for Band V WRITE_2G_RESTORE 0x0c420653 // rx_Cload_HB = 6 for Band III, 5 for Band II, & 3 for Band I WRITE_2G_RESTORE 0x090502b9 // o_tx_PrePaCC=1 //////////////////////////////////////// // IQLOFT //////////////////////////////////////// WRITE_3G_PREIQLOFT 0x00184505 WRITE_3G_PREIQLOFT 0x02242488 WRITE_3G_PREIQLOFT 0x03770049 WRITE_3G_PREIQLOFT 0x03783000 WRITE_3G_PREIQLOFT 0x045a0200 WRITE_3G_PREIQLOFT 0x045c0008 WRITE_3G_PREIQLOFT 0x045e000b WRITE_3G_PREIQLOFT 0x045f03ff WRITE_3G_PREIQLOFT 0x04660000 WRITE_3G_PREIQLOFT 0x04670000 WRITE_3G_PREIQLOFT 0x04680000 WRITE_3G_PREIQLOFT 0x046a0007 WRITE_3G_PREIQLOFT 0x046b0100 WRITE_3G_PREIQLOFT 0x046c0400 WRITE_3G_PREIQLOFT 0x046d0001 WRITE_3G_PREIQLOFT 0x04722000 WRITE_3G_PREIQLOFT 0x04920000 WRITE_3G_PREIQLOFT 0x04940000 WRITE_3G_PREIQLOFT 0x04fc0400 WRITE_3G_PREIQLOFT 0x0816ffff WRITE_3G_PREIQLOFT 0x0902566c WRITE_3G_PREIQLOFT 0x090506c9 WRITE_3G_PREIQLOFT 0x09095003 WRITE_3G_PREIQLOFT 0x09130000 WRITE_3G_PREIQLOFT 0x092200f0 WRITE_3G_PREIQLOFT 0x092f5fa6 WRITE_3G_PREIQLOFT 0x09304611 WRITE_3G_PREIQLOFT 0x09c02901 // BAND idx xfact0(2G) xfact1(3G) rcy 0x0454 0x0455 0x0458 0x0468 0x046b 0x0494 0x049e 0x049f 0x0902 0x0904 0x0906 0x0907 0x0909 0x0909 0x090a 0x090f 0x0910 // ==== === ========== ========== ==== ====== ====== ====== ====== ====== ====== ====== ====== ====== ====== ====== ====== ====== ====== ====== ====== ====== WRITE_3G_IQLOFT UMTSLB 0 0xFFFFFFFF 0x0000FFFF 0 0x0c41 0x003e 0x0100 0x0000 0x0100 0x0000 0x3c1e 0x412e 0x0566f 0x00a0 0x00b8 0x80ff 0x5803 0x5803 0x0019 0x0007 0x8fef WRITE_3G_IQLOFT UMTSLB 1 0x00000000 0x00010000 1 0x0c41 0x003e 0x0100 0x0000 0x0100 0x0000 0x3c0a 0x412e 0x0566f 0x0090 0x00ae 0x80ff 0x5803 0x5803 0x0011 0x0007 0x8fef WRITE_3G_IQLOFT UMTSLB 2 0x00000000 0x00020000 1 0x0c41 0x003e 0x0100 0x0000 0x0100 0x0000 0x3c0a 0x523a 0x0566f 0x0090 0x00c6 0x80ff 0x5803 0x5803 0x0011 0x0007 0x8fef WRITE_3G_IQLOFT UMTSLB 3 0x00000000 0x00040000 1 0x0c42 0x002d 0x0100 0x0000 0x0100 0x3000 0x3c0a 0x9266 0x0566f 0x00b0 0x00e2 0x86f9 0x5803 0x5803 0x0011 0x0007 0x8fef WRITE_3G_IQLOFT UMTSLB 4 0x00000000 0x00380000 1 0x0c42 0x002d 0x0100 0x0000 0x0100 0x3000 0x3c0a 0x9266 0x0566f 0x00dd 0x00ee 0x86f9 0x5803 0x5803 0x0011 0x0007 0x8fef WRITE_3G_IQLOFT UMTSLB 5 0x00000000 0x00400000 0 0x0c42 0x002d 0x0000 0x0005 0x00fa 0x3000 0x3c14 0x291d 0x0566f 0x0080 0x00ec 0x80ff 0x5003 0x5003 0x0011 0x0000 0xffef WRITE_3G_IQLOFT UMTSLB 6 0x00000000 0x01800000 0 0x0c42 0x002d 0x0000 0x0005 0x00fa 0x3000 0x3c14 0x4934 0x0566f 0x0080 0x00f4 0x80ff 0x5003 0x5003 0x0011 0x0000 0xffef WRITE_3G_IQLOFT UMTSLB 7 0x00000000 0xFE000000 1 0x0c44 0x002d 0x0000 0x0005 0x00fa 0x3000 0x3c0a 0x825b 0x0566f 0x0080 0x00f6 0x99e6 0x5003 0x5003 0x0011 0x0000 0xffef WRITE...
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