m8cinstructions.pdf

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Program Flow Instructions
CALL
9xh
CALL addr
HALT
30h
HALT
JACC
Exh JACC addr
JC
Cxh JC addr
JMP
8xh
JMP addr
JNC
Dxh JNC addr
JNZ
Bxh JNZ addr
JZ
Axh JZ addr
LCALL
7Ch LCALL addrl
LJMP
7Dh LJMP addrl
NOP
40h
NOP
RET
7Fh RET
RETI
7Eh RETI
SSC
00h
SSC
Non Destructive Test Instructions
CMP
39h
CMP A,expr
3Ah CMP A,[expr]
3Bh CMP A,[X+exr]
3Ch CMP [expr],expr
3Dh CMP [X+expr],expr
TST
47h
TST [expr],expr
48h
TST [X+expr],expr
49h
TST REG[expr],expr
4Ah TST REG[X+expr],expr
Arithmetic Instructions
ADC
09h
ADC A,expr
0Ah ADC A,[expr]
0Bh ADC A,[X+expr]
0Ch ADC [expr],A
0Dh ADC [X+expr],A
0Eh ADC [expr],expr
0Fh ADC [X+expr],expr
ADD
01h
ADD A,expr
02h
ADD A,[expr]
03h
ADD A,[X+expr]
04h
ADD [expr],A
05h
ADD [X+expr],A
06h
ADD [expr],expr
07h
ADD [X+expr],expr
38h
ADD SP,expr
SBB
19h
SBB A,expr
1Ah SBB A,[expr]
1Bh SBB A,[X+expr]
1Ch SBB [expr],A
1Dh SBB [X+expr],A
1Eh SBB [expr],expr
1Fh SBB [X+expr],expr
SUB
11h
SUB A,expr
12h
SUB A,[expr]
13h
SUB A,[X+expr]
14h
SUB [expr],A
15h
SUB [X+expr],A
16h
SUB [expr],expr
17h
SUB [X+expr],expr
DEC
78h
DEC A
79h
DEC X
7Ah DEC [expr]
7Bh DEC [X+expr]
INC
74h
INC A
75h
INC X
76h
INC [expr]
77h
INC [X+expr]
ASL
64h
ASL A
65h
ASL [expr]
66h
ASL [X+expr]
ASR
67h
ASR A
68h
ASR [expr]
69h
ASR [X+expr]
Flags
Call (relative)
LSB Address Byte (MSN in opcode, x)
Halt
Jump Accumulator (relative)
LSB Address Byte (MSN in opcode, x)
Jump if Carry (relative)
LSB Address Byte (MSN in opcode, x)
Jump (relative)
LSB Address Byte (MSN in opcode, x)
Jump if No Carry (relative)
LSB Address Byte (MSN in opcode, x)
Jump if Not Zero (relative)
LSB Address Byte (MSN in opcode, x)
Jump if Zero (relative)
LSB Address Byte (MSN in opcode, x)
Long Call
addr MSB
Long Jump
addr MSB
No Operation
Return from Call
Cycles
11
NA
Cypress MicroSystems
M8C Instruction Set Summary
Movement Instructions
INDEX
Fxh
INDEX addr
MOV
4Fh
MOV X,SP
50h
MOV A,expr
51h
MOV A,[expr]
52h
MOV A,[X+expr]
53h
MOV [expr],A
54h
MOV [X+expr],A
55h
MOV [expr],expr
56h
MOV [X+expr],expr
57h
MOV X,expr
58h
MOV X,[expr]
59h
MOV X,[X+expr]
5Ah MOV [expr],X
5Bh MOV A,X
5Ch MOV X,A
5Dh MOV A,REG[expr]
5Eh MOV A,REG[X+expr]
5Fh
MOV [expr],[expr]
60h
MOV REG[expr],A
61h
MOV REG[X+expr],A
62h
MOV REG[expr],expr
63h
MOV REG[X+expr],expr
MVI
3Eh MVI A,[expr]
3Fh
MVI [expr],A
POP
18h
POP A
20h
POP X
PUSH
08h
PUSH A
10h
PUSH X
ROMX
28h ROMX
SWAP
4Bh SWAP A,X
4Ch SWAP A,[expr]
4Dh SWAP X,[expr]
4Eh SWAP A,SP
Logical Instructions
AND
21h
AND A,expr
22h
AND A,[expr]
23h
AND A,[X+expr]
24h
AND [expr],A
25h
AND [X+expr],A
26h
AND [expr],expr
27h
AND [X+expr],expr
41h
AND REG[expr],expr
42h
AND REG[X+expr],expr
70h
AND F,expr
OR
29h
OR A,expr
2Ah OR A,[expr]
2Bh OR A,[X+expr]
2Ch OR [expr],A
2Dh OR [X+expr],A
2Eh OR [expr],expr
2Fh
OR [X+expr],expr
43h
OR REG[expr],expr
44h
OR REG[X+expr],expr
71h
OR F,expr
XOR
31h
XOR A,expr
32h
XOR A,[expr]
33h
XOR A,[X+expr]
34h
XOR [expr],A
35h
XOR [X+expr],A
36h
XOR [expr],expr
37h
XOR [X+expr],expr
45h
XOR REG[expr],expr
46h
XOR REG[X+expr],expr
72h
XOR F,expr
CPL
73h
CPL A
RLC
6Ah RLC A
6Bh RLC [expr]
6Ch RLC [X+expr]
RRC
6Dh RRC A
6Eh RRC [expr]
6Fh
RRC [X+expr]
Flags
Table Read (relative)
LSB Address Byte (MSN in opcode, x)
Move
Immediate
Direct Address
Index
Direct Address
Index
Direct Address
Index
Immediate
Direct Address
Index
Direct Address
z
Cycles
13
4
4
5
6
5
6
8
9
4
6
7
5
4
4
6
7
10
5
6
8
9
10
10
5
5
4
4
Table Read
z
Swap
Direct Address
Direct Address
z
z
z
z
Flags
Bitwise AND
Immediate
Direct Address
Index
Direct Address
Index
Direct Address
Index
Reg Direct Address
Reg Index
Immediate
Bitwise OR
Immediate
Direct Address
Index
Direct Address
Index
Direct Address
Index
Reg Direct Address
Reg Index
Immediate
Bitwise XOR
Immediate
Direct Address
Index
Direct Address
Index
Direct Address
Index
Reg Direct Address
Reg Index
Immediate
Complement Accumulator
Rotate Left through Carry
Direct Address
Index
Rotate Right through Carry
Direct Address
Index
cz
cz
cz
cz
cz
cz
4
7
8
4
7
8
z
z
z
z
z
z
z
z
z
cz
z
z
z
z
z
z
z
z
z
cz
z
z
z
z
z
z
z
z
z
cz
z
5
7
7
5
Cycles
4
6
7
7
8
9
10
9
10
4
4
6
7
7
8
9
10
9
10
4
4
6
7
7
8
9
10
9
10
4
4
11
7
5/4
5
5/4
5/4
5/4
addr LSB
addr LSB
13
7
4
8
z
z
z
Immediate
Immediate
z
Reg Direct Address
Reg Index
Direct Address
Reg Direct Address
Reg Index
Reg Direct Address
Reg Index
Move Indirect, Post Increment to Memory
Direct Address (Page 0)
Direct Address (Page 0)
Pop Stack into Register
z
z
Direct Address
Return from Interrupt
System Supervisor Call
10
NA
Immediate
Immediate
z
Non Destructive Compare
Immediate
Direct Address
Index
Direct Address
Index
Test with Mask
Direct Address
Index
Reg Direct Address
Reg Index
Immediate
Immediate
Bit Mask
Bit Mask
Bit Mask
Bit Mask
cz
cz
cz
cz
cz
z
z
z
z
Flags
5
7
8
8
9
8
9
8
9
Cycles
4
6
7
7
8
9
10
4
6
7
7
8
9
10
5
4
6
7
7
8
9
10
4
6
7
7
8
9
10
4
4
7
8
4
4
7
8
4
7
8
4
7
8
z
Push Register onto Stack
Add with Carry
Immediate
Direct Address
Index
Direct Address
Index
Direct Address
Index
Add without Carry
Immediate
Direct Address
Index
Direct Address
Index
Direct Address
Index
Immediate
Subtract with Borrow
Immediate
Direct Address
Index
Direct Address
Index
Direct Address
Index
Subtract without Borrow
Immediate
Direct Address
Index
Direct Address
Index
Direct Address
Index
Decrement
Immediate
Immediate
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
cz
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Immediate
Direct Address
Index
Increment
Direct Address
Index
Arithmetic Shift Left
Direct Address
Index
Arithmetic Shift Right
Direct Address
Index
From CY8C25xxx/26xxx Data Sheet CMS10002A-R1.14
Copyright
2000-2001 Cypress MicroSystems, Inc.

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