PACDesigner software.pdf

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PAC-Designer
Software
ispPAC
TM
Development System
Features
• FULLY INTEGRATED DESIGN AND SIMULATION
ENVIRONMENT FOR IN-SYSTEM PROGRAMMABLE
ANALOG CIRCUIT (ispPAC) DEVICE DESIGN
• GRAPHICAL USER INTERFACE
— Easy-to-Use Design and Simulation GUI
• DESIGN ENTRY
— Schematic Entry for Internal Connections and for
Setting Parametric Circuit Values
— Standard Circuit Generation Macros
• Biquad Filter
• Ladder Filter
• SIMULATION
— Observe Both Gain and Phase Plots Graphically
— Display Up to Four Combinations of Inputs and
Outputs Simultaneously
— Simulator Options Dialog Box
— Cross Hair Cursor to Directly Read Any Gain or
Phase Magnitude on the Simulation Plots
• SUPPORTS ALL LATTICE ispPAC DEVICES
• STARTER AND SYSTEM VERSIONS AVAILABLE
— System Version Supports All Available Functions
— Starter Version Supports All Functions Except
In-System Programming
• PLATFORMS
— Windows
®
95, Windows 98, Windows NT
®
4.0
TM
Flow and Design Environment
PAC-Designer is a self-contained analog design devel-
opment system. Entry, macro implementation, simulation
and programming are all completed from within the
Microsoft Windows-based PAC-Designer. Toolbars and
drop down menus provide the user with easy access to all
the features of PAC-Designer. Design control, such as
pin connection, gain and capacitor value selection, is
easily accomplished through point-and-click or drag-
and-drop operations, or through dialog boxes, as
appropriate. Gain and capacitor values are automatically
displayed on the schematic and design report files can be
generated for user convenience and documentation.
To help in the implementation of the design, Lattice also
supplies with the PAC-Designer Base System an
ispPAC10 Evaluation Board and ispDOWNLOAD™ cable
that allow the user to program the ispPAC device and use
an oscilloscope to observe operation.
The PAC-Designer development flow is shown in Figure 1.
Design Entry
The PAC-Designer schematic window provides access
to all configurable ispPAC10 elements via its graphical
user interface. All input and output pins are represented.
Any element in the schematic window can be accessed
via mouse operations or menu commands. When com-
pleted, configurations can be saved, simulated and
downloaded to devices.
For example, gain parametric values applied to each
input are selected by positioning the mouse pointer
above the input stage symbol (IA1...8). Double clicking
on a number will cause the polarity/gain level dialog box
to open. Any value from -10 to +10 can be selected from
the list of choices.
Introduction
Lattice Semiconductor ispPAC10 In-System-Program-
mable (ISP™) Analog Circuits allow designers to build
analog circuits such as gain stages and active filters
without the use of external feedback resistors or capaci-
tors. Device functionality and characteristics, such as
gain and frequency response, can be set using the PAC-
Designer Development System.
PAC-Designer has a graphical design entry interface that
allows complete control over the configuration of ispPAC
products. Design entry consists of making internal con-
nections and choosing parametric circuit values. When
complete, the circuit can be simulated, saved and down-
loaded to an ispPAC10 device. To accelerate design
development, standard circuit functions are available
from a library of common designs.
Cursor Feedback
Configurable ispPAC elements are either parametric
values (gain/polarity, feedback, capacitors, etc.) or inter-
connect options. In an active schematic window, the
appearance of the cursor provides visual feedback about
which operations are possible for a given location.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-888-477-7537; FAX (503) 268-8037; http://www.latticesemi.com
September 1999
pacdes_01
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PAC-Designer Software
Figure 1. PAC-Designer Development Flow
ispPAC10
Evaluation Board
Simulator
Design
Entry
ispPAC10
PAC
Library
PAC
Macros
.TXT
.CSV
Report
Files
.SVF
.JED
Programming
Files
Editing Symbols
In addition to the point-and-click method for editing the
schematic window, menu commands exist for editing all
portions of a design. Access to all connections and
parametric values, such as gain and capacitors, can be
obtained by using the Edit => Symbol menu command
and then selecting the item to be edited.
Simulation
PAC-Designer has built-in simulation capability and can
display AC gain/phase plots for user-selected input to
output combinations.
After a design has been configured, it may be simulated
to verify performance and compare operation to ex-
pected results. The simulator can also be used during
design entry to try various options or compare alternate
configurations. The simulator is capable of computing
and displaying the AC response of up to four combina-
tions of inputs to outputs at once. Simulations can be
performed at any time after a path exists between at least
one input pin and any output.
Once a design is completed, or at least the initial connec-
tions have been made, a simulation plot can be initiated
by pressing the Run Simulator button on the toolbar. It
can also be initiated by using the Tools => Run Simulator
menu command.
Design Library
A group of files made up of preconfigured designs is
located in a subdirectory labeled \LIBRARY under the
main directory containing PAC-Designer. Files stored in
this directory can be browsed for summary information
using the File => Browse Library menu command. The
library contains possible implementations of common
analog functions. These circuits demonstrate basic tech-
niques and can serve as starting points for more complex
designs. In addition to reference designs placed here
during the install procedure, users may place their own
reference designs here for easy future access.
PAC-Designer Circuit Generator Macros, such as the
ladder or biquad filter generators, are included as well.
These macros allow you to select your circuit configura-
tion (e.g. filter frequency) from a simple pull-down menu
to quickly complete your design.
Active Curve
Only one plot curve is considered active at any given
time. The active curve can be changed by pressing any
of the deselected curve buttons on the toolbar, by clicking
on the corresponding curve presence indicator in a plot
window or by selecting the Curve => Activate menu
command when a plot window is active.
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PAC-Designer Software
Figure 2. PAC-Designer Toolbar, Schematic Window
New
Open
Save
Print
Zoom Controls
Activate Simulation Curves 1-4
Run
Download
Simulator
Figure 3. PAC-Designer Toolbar, Plot Window
Zoom Controls
Cross Hair
Figure 4. PAC-Designer Menu Structure, Schematic Window
File
Edit
View
Tools
Options
Window
Help
Figure 5. PAC-Designer Menu Structure, Plot Window
File
Edit
View
Curve
Tools
Options
Window
Help
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PAC-Designer Software
Only the active curve is updated when the Tools => Run
Simulator menu command is chosen or the Run Simula-
tor toolbar button is pressed. Conditions for each
simulation are determined by settings made under the
Options => Simulator menu command. To update more
than one curve in a plot window, each must be activated
and then updated individually.
The Verify command causes the configuration stored in
an ispPAC device to be read and compared to the current
design without making changes. The verify option is
accessed by selecting Tools => Verify.
Both operations can be initiated anytime PAC-Designer
is running and there is an open design file.
Simulator Options
Simulation options for each of the four possible curves
per plot can be accessed through the simulator options
dialog box, opened by the Options => Simulator menu
command. A checkbox at the bottom of the window
provides the option of recalculating the active curve each
time any item in the schematic window is changed.
JTAG IDCODE
All ispPAC devices contain an internal 32-bit JTAG
identification code unique for each device type. It is
possible to read the JTAG optional IDCODE string from
any device that contains such identification.
User Electronic Signature
Within ispPAC devices, bits are made available for stor-
ing user-specific information. These are called UES bits.
These bits can be used to store device configuration,
design data or any information the user wishes to retain
with the individual device. For the ispPAC10, eight bits
are available for user configuration and are set by select-
ing the Edit => Symbol menu command and scrolling
down to the UES line and pressing ‘EDIT.’
Gain and Phase Readout
It is possible to directly read the gain and phase magni-
tude for any point along a plot by using the cross hair
cursor feature. The cursor within a plot window is acti-
vated by pressing the Activate Cross Hair toolbar button
or by selecting the View => Cross Hair menu command.
When activated, a readout of gain and phase versus
frequency appears in the lower right-hand corner (status
bar) of the main window
Security
A bit can be set inside an ispPAC device to prevent all
future upload or verify operations. The security bit pro-
vides an option to prevent unauthorized access to a
device. Once set and loaded to a device via a download
operation, the only way it can be changed is by repro-
gramming the device. Setting the security bit is performed
by selecting the Edit => Security menu command.
Device Programming
A unique feature of the ispPAC product family is in-
system programmability that allows devices to be
programmed in-circuit, directly on the application board.
PAC-Designer generates all programming signals when
properly connected to an in-circuit device. The program-
ming interface of the ispPAC10 is the IEEE 1149.1-1990
JTAG test access port (TAP).
ispDOWNLOAD Cable
Once the design is completed, the user can immediately
download the configuration to the ispPAC device while it
is soldered to the board. This is accomplished using the
ispDOWNLOAD cable connected to the PC parallel port.
The software automatically generates the necessary
timing and signals for the JTAG interface and the ispPAC
device.
Download
Any design configuration created in the System version
of PAC-Designer can be downloaded to an ispPAC
device. (The Starter version does not include program-
ming). Programming download is accomplished by
pressing the Download button on the toolbar or by select-
ing the Tools => Download menu command. Programming
circuitry in the ispPAC device is then enabled and the
configuration is stored in E
2
CMOS
®
memory on the chip.
This process takes approximately 100ms.
Design Documentation
Once a design has been configured, PAC-Designer
contains many helpful features to save and retrieve
configuration information in various formats. Designs
and simulations can be documented via several printout
options. These export, import and printing alternatives
include:
Upload and Verify Operations
The upload operation is accessed via the Tools =>
Upload menu command. When executed, the configura-
tion stored in the ispPAC device is read and transferred
to the schematic window of the current design.
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PAC-Designer Software
• Printouts
• Export and Import
• Schematic Files
• Plot Files
To run PAC-Designer software efficiently, a system com-
prised of the following hardware and software is
recommended:
Hardware
• An 80486 or Pentium-based IBM or compatible
computer
• At least 16 megabytes of memory
• A hard disk with 10 megabytes of free space
(typical installation)
• Printer parallel port to accommodate
ispDOWNLOAD cable
Software
• Microsoft Windows 95, Windows 98 or
Windows NT 4.0 (Service Pack 3)
System Requirements
Printouts
Print options can be accessed via the File => Page Setup
command when a schematic or plot window is active. The
page setup dialog box allows page headers, a comments
field and the field name, date and time to be included in
the printout. Options to print in color or black and white
are available, as well as to print on one or two pages or
to combine more than one plot on the same graph.
Export and Import
PAC-Designer can export alternative forms of schematic
and plot data. This information can be used for design
documentation, importing into third-party software such
as a spreadsheet for graphing, or as in the case of an SVF
file (JTAG serial vector format), data to program or read
from devices in a JTAG serial chain. Export and import
operations are initiated using the File => Export or File =>
Import menu commands.
Package Contents
PAC-System 10
• Complete PAC-Designer Software on CD-ROM
• Getting Started Manual
• Install Guide
• ispDOWNLOAD Cable
• ispPAC Device Evaluation Board
• ispPAC10-01PI Samples (2)
• Perpetual License (Contact Lattice Semiconductor)
• One-Year Maintenance
PAC-Starter
• PAC-Designer Software on CD-ROM (Supports All
Aspects of Design Except Device Programming)
• Six-Month License
PAC10-EV
• ispPAC10 Device Evaluation Board
• ispPAC10-01PI Samples (2)
Schematic File
The Schematic File outputs a listing of all the config-
urable items in the ispPAC device and lists their value or
setting. The file also includes summary information fields
that allow the user to maintain pertinent design informa-
tion such as title, author, subject, keywords and comments.
Plot File
The plot (.csv) file includes comma-separated values
representing the plot (gain/phase) data of the current
design. The plot file can be generated by PAC-Designer
or the user may import a plot file to PAC-Designer as a
design entry method.
ispPAC10 Evaluation Board
The ispPAC10 Evaluation Board allows the user to quickly
configure and evaluate the ispPAC10 on a fully as-
sembled PC board. The double-sided board supports a
28-pin DIP package, connectors for Input and Output
signals, a JTAG programming cable interconnect and a
prototype array section for additional circuitry to be
added by the user. In-system programming is accom-
plished through the JTAG port. The JTAG signals are
driven from the parallel port of a PC through an
ispDOWNLOAD™ cable. The Evaluation Board inter-
faces to a signal source or other test equipment through
the BNC connectors.
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