Acer Aspire AOD255 ddr3 la-6421p.pdf

(944 KB) Pobierz
A
B
C
D
E
1
1
Compal Confidential
2
2
PAV70 DDR3 Schematics Document
Intel Pineview Processor with Tigerpoint + DDRIII
2010-06-25
3
3
REV: 1.0
4
4
Security Classification
Issued Date
2006/08/18
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
2007/8/18
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Cover Page
Size
B
Date:
Document Number
LA-6421P
Friday, June 25, 2010
E
Rev
0.1
1
of
39
Sheet
A
B
C
D
E
Compal Confidential
Model Name : PAV50
File Name : LA-6421P
1
Clock Generator
CK505
page 8
CRT Conn
page 10
ZZZ
1
RGB
PCB
DA60000I610
LCD Conn.
page 9
LVDS
Pineview
FCBGA 559
22x22mm
page 4,5,6
Memory BUS(DDRIII)
DDRIII-SO-DIMM
page 7
1.5V DDRIII 667
Thermal Sensor
EMC1402
page 5
DMI
X2 mode
GEN1
2
PCI-Express
Tigerpoint
PCBGA360
LPC BUS
TPM
page 27
USB
HDA
SATA
USB Port x2(L)
page 20
2
BlueTooth
page 15
17x17mm
page 11,12,13,14
MINI Card x1
3G
page 15
WLAN
page 26
10/100 Ethernet
AR8152
page 25
CMOS CAM
HDD
page 16
page 9
3G
page 15
Transfermer
3
LPC BUS
USB Port x1(R)
RJ45
Power ON/OFF
page 18
Aralia Codec
ALC272
page 22
page 20
3
DC/DC Interface
page 29
Card Reader
ENE6252
page 25
3VALW/5VALW
page 33
Int.KBD
page 19
DC IN
page 30
ENE KBC
KB926
page
SPI
17
1.5VP/VCCP
BATT IN
page 34
page 31
CHARGER
4
page 32
0.89VP/1.8VP
0.75VS
page 35
SPI ROM
Light Sensor
page27
AMP & INT
Speaker
INT MIC
HeadPhone &
MIC Jack
SD/MMC/MS
CONN
Touch Pad
page19
page 17
4
CPU_CORE
page 36
Security Classification
Issued Date
2006/08/18
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
2007/8/18
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Block Diagrams
Size
B
Date:
Document Number
LA-6421P
Friday, June 25, 2010
E
Rev
0.1
2
of
39
Sheet
A
B
C
D
E
1
1
Voltage Rails
Power Plane
VIN
B+
+CPU_CORE
+0.75VS
+VCCP
+1.5VS
+1.5V
+0.89V
+3VALW
+3VS
+5VALW
2
External PCI Devices
Description
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
0.75V switched power rail for DDR terminator
VCCP switched power rail
1.5V switched power rail
1.5V power rail for DDR
Graphic core power rail
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
VSB always on power rail
RTC power
S1
N/A
N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
S3
N/A
N/A
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
S5
N/A
N/A
OFF
OFF
OFF
OFF
OFF
OFF
ON*
OFF
ON*
OFF
ON*
ON
2
DEVICE
IDSEL #
REQ/GNT #
PIRQ
No PCI Device
+5VS
+VSB
+RTCVCC
EC SM Bus1 address
Device
Address
0001 011X b
Smart Battery
EC SM Bus2 address
Device
EMC1402
Address
100_1100
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
STATE
Full ON
SIGNAL
SLP_S3# SLP_S4# SLP_S5#
HIGH
HIGH
LOW
LOW
LOW
HIGH
HIGH
HIGH
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
+VALW
ON
ON
ON
ON
ON
+V
ON
ON
ON
OFF
OFF
+VS
ON
ON
OFF
OFF
OFF
Clock
ON
LOW
OFF
OFF
OFF
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
3
ICH7M SM Bus address
BOARD ID Table(Page 17)
VCC
Ra
Device
Clock Generator
(SLG8SP556VTR)
DDR DIMMA
3
Address
1101 001Xb
1010 000Xb
3.3V
100K
Rb
Vab-Min
Vab-Typ
Vab-Max
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
R01 (EVT)
R02 (DVT)
R03 (PVT)
R10A (MP)
ID BRD ID
PAV50
0
1
2
3
4
5
6
7
0
8.2K
18K
33K
56K
100K
200K
NC
0V
0.216V
0.436V
0.712V
1.036V
1.453V
1.935V
2.500V
0V
0.250V
0.503V
0.819V
1.185V
1.650V
2.200V
3.3V
0V
0.289V
0.538V
0.875V
1.264V
1.759V
2.341V
3.3V
4
4
Security Classification
Issued Date
2006/08/18
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
2007/8/18
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
Notes List
Size
B
Date:
Document Number
LA-6421P
Monday, May 03, 2010
E
Rev
0.1
3
of
39
Sheet
5
4
3
2
1
(7) DDR_A_DQS#[0..7]
U71
U71A
PINEVIEW_M
PINEVIEW_M
N475@
(7) DDR_A_D[0..63]
U71B
N475@
REV = 1.1
(7) DDR_A_DM[0..7]
REV = 1.1
N455@
DMI_RX0_R
DMI_RX#0_R
DMI_RX1_R
DMI_RX#1_R
F3
F2
H4
G3
DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
DMI
DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1
G2
G1
H3
J2
DMI_TX0 (13)
DMI_TX#0 (13)
DMI_TX1 (13)
DMI_TX#1 (13)
(7) DDR_A_DQS[0..7]
(7) DDR_A_MA[0..14]
D
(8) CLK_CPU_EXP#
(8) CLK_CPU_EXP
N7
N6
R10
R9
N10
N9
EXP_CLKINN
EXP_CLKINP
EXP_TCLKINN
EXP_TCLKINP
RSVD
RSVD
EXP_RCOMPO
EXP_ICOMPI
EXP_RBIAS
RSVD_TP
RSVD_TP
L10
L9
L8
N11
P11
R162
R203 49.9_0402_1%
750_0402_1%
T38
T39
DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
AH19
AJ18
AK18
AK16
AJ14
AH14
AK14
AJ12
AH13
AK12
AK20
AH12
AJ11
AJ24
AJ10
AK22
AJ22
AK21
AJ20
AH20
AK11
Must be placed within 500 mils from Pineview-M pins
(7) DDR_A_WE#
(7) DDR_A_CAS#
(7) DDR_A_RAS#
(7) DDR_A_BS0
(7) DDR_A_BS1
(7) DDR_A_BS2
DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14
DDR_A_WE#
DDR_A_CAS#
DDR_A_RAS#
DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2
DDR_A_DQS_0
DDR_A_DQS#_0
DDR_A_DM_0
DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7
DDR_A_DQS_1
DDR_A_DQS#_1
DDR_A_DM_1
DDR_A_DQ_8
DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15
DDR_A_DQS_2
DDR_A_DQS#_2
DDR_A_DM_2
DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23
DDR_A_DQS_3
DDR_A_DQS#_3
DDR_A_DM_3
DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
DDR_A_DQS_4
DDR_A_DQS#_4
DDR_A_DM_4
DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39
DDR_A_DQS_5
DDR_A_DQS#_5
DDR_A_DM_5
DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47
DDR_A_DQS_6
DDR_A_DQS#_6
DDR_A_DM_6
DDR_A
AD3
AD2
AD4
AC4
AC1
AF4
AG2
AB2
AB3
AE2
AE3
AB8
AD7
AA9
AB6
AB7
AE5
AG5
AA5
AB5
AB9
AD6
AD8
AD10
AE8
AG8
AG7
AF10
AG11
AF7
AF8
AD11
AE10
AK5
AK3
AJ3
AH1
AJ2
AK6
AJ7
AF3
AH2
AL5
AJ6
AG22
AG21
AD19
AE19
AG19
AF22
AD22
AG17
AF19
AE21
AD21
AE26
AG27
AJ27
AE24
AG25
AD25
AD24
AC22
AG24
AD27
AE27
AE30
AF29
AF30
AG31
AG30
AD30
AD29
AJ30
AJ29
AE29
AD28
AB27
AA27
AB26
AA24
AB25
W24
W22
AB24
AB23
AA23
W27
DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DM0
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DM1
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DM2
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DM3
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DM4
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DM5
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DM6
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DM7
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
A
D
U71
K2
J1
M4
L3
N550@
RSVD
RSVD
RSVD
RSVD
PINEVIEW-M_FCBGA8559
1 OF 6
RSVD
RSVD
RSVD
RSVD
K3
L2
M2
N2
JP16
(5)
(5)
(5)
(5)
(13)
(13)
C
(7) DDR_CS#0
(7) DDR_CS#1
CONN@
(7) DDR_CKE0
(7) DDR_CKE1
DDR_CS#0
DDR_CS#1
XDP_PREQ#
XDP_PRDY#
XDP_BPM#3
XDP_BPM#2
XDP_BPM#1
XDP_BPM#0
R354
1
R347
1
CPU_ITP
CPU_ITP#
XDP_PREQ#
XDP_PRDY#
XDP_BPM#3
XDP_BPM#2
XDP_BPM#1
XDP_BPM#0
@
1K_0402_5%
2
@2
1K_0402_5%
DMI_RX0
DMI_RX#0
DMI_RX1
DMI_RX#1
C435
C436
C437
C438
1
1
1
1
DMI_RX0_R
2
0.1U_0402_10V7K
DMI_RX#0_R
2
0.1U_0402_10V7K
DMI_RX1_R
2
0.1U_0402_10V7K
DMI_RX#1_R
2
0.1U_0402_10V7K
(5)
(5)
(5,13) H_PWRGD
(13)
SLPIOVR#
(13)
(13)
(8)
(8)
+VCCP
(5,13,15,17,25,26,27)
PLTRST#
(5)
(5)
(5)
(5)
(5)
PLTRST#
1
R348
@2
1K_0402_1%
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCK
Close to CPU
2010-1-18 modify
+1.5V
2
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2
AH22
AK25
AJ21
AJ25
AH10
AH9
AK10
AJ8
AK24
AH26
AH24
AK27
DDR_A_CS#_0
DDR_A_CS#_1
DDR_A_CS#_2
DDR_A_CS#_3
DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3
DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3
DDR_CKE0
DDR_CKE1
(7) M_ODT0
(7) M_ODT1
M_ODT0
M_ODT1
C
(7)
(7)
(7)
(7)
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
AG15
AF15
AD13
AC13
AC15
AD15
AF13
AG13
DDR_A_CK_0
DDR_A_CK_0#
DDR_A_CK_1
DDR_A_CK_1#
DDR_A_CK_3
DDR_A_CK_3#
DDR_A_CK_4
DDR_A_CK_4#
(7) DRAM_PWROK
DRAM_PWROK
ACES_87151-24051
AD17
AC17
AB15
AB17
+VCCP
@
1
R1412
10K_0402_5%
XDP Reserve
XDP_TDI
XDP_TMS
R341
1
R342
1
R343
1
R344
1
2
2
2
2
DRAMRST# (7)
XDP_TDO
XDP_PREQ#
2010/01/18 DDR3 add
+1.5V
+1.5V
2
DRAM_PWROK
AB4
DRAMRST#_R
AK8
R370
0_0402_5%
@
T40
T41
RSVD
RSVD
RSVD
RSVD
51 +-1% 0402
51 +-1% 0402
51 +-1% 0402
51 +-1% 0402
R1413
DRAMRST#_R
1
2
DRAMRST#
0_0402_5%
B
0.1U_0402_10V7K
R50
1K_0402_1%
2
1
RSVD
RSVD
1
AB11
AB13
AL28
AK28
AJ26
AK29
RSVD_TP
RSVD_TP
DDR_VREF
DDR_RPD
DDR_RPU
RSVD
B
XDP_TRST#
FAN1 Conn
Modify follow KAV60 schematic 06/12
+5VS
XDP_TCK
R345
1
R346
1
2
2
51 +-1% 0402
51 +-1% 0402
R142
1K_0402_1%
2
2
R243
R242 80.6_0402_1%
80.6_0402_1%
2
C440
0.01U_0402_16V7K
1
C439
1
1
+5VS
C312
1
U12
+VCC_FAN1
1
2
R47
330_0402_5%
1
C1151
+3VS
0.01U_0402_16V7K
1
1
2
3
4
EN
VIN
VOUT
VSET
GND
GND
GND
GND
8
7
6
5
1
1
2
C314
2.2U_0603_10V6K
2
3
2
D19
@
DAN217_SC59
Modify D38 D39 D40 Pin define
XDP_TMS
XDP_TCK
3
XDP_PREQ#
XDP_TDO
3
2
D39
PJDLC05C_SOT23-3
4.7U_0603_6.3V6K
C313
1
2
XDP_TRST#
XDP_TDI
3
2
D40
PJDLC05C_SOT23-3
2
08/13
DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55
DDR_A_DQS_7
DDR_A_DQS#_7
DDR_A_DM_7
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63
2 OF 6
D38
(17)
EN_FAN1
APL5607KI-TRG_SO8
4.7U_0603_6.3V6K
C1150
1000P_0402_50V7K
1
2
2
A
R256
10K_0402_5%
PJDLC05C_SOT23-3
1
1
40mil
2
+VCC_FAN1
(17) FAN_SPEED1
1
C311
3G@
100P_0402_50V8J
1
2
3
PINEVIEW-M_FCBGA8559
1
2
3
G1
G2
4
5
1
JP12
Add 2009-6-17
ACES_85204-03001
CONN@
Security Classification
Issued Date
2006/08/18
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
2007/8/18
Title
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
3
2
Pineview(1/3)
Size Document Number
Custom
Date:
Monday, June 28, 2010
1
LA-6421P
Sheet
4
of
39
Rev
0.1
5
4
3
2
1
Add 470PF on H_SMI# for known issue 07/08
PINEVIEW_M
U71C
N475@
R249
1
1
R247
15_0402_5%
2
2
15_0402_5%
@
1
GMCH_CRT_HSYNC
GMCH_CRT_VSYNC
(10)
(10)
U71D
PINEVIEW_M
C1171
D
R1378
1
2
T8
1K_0402_5% T15
T9
T16
T10
T17
T11
T28
VGA
T2
T12
T3
T4
T13
T5
T6
T7
T14
D12
A7
D6
C5
C7
C6
D8
B7
A9
D9
C8
B8
C10
D10
B11
B10
B12
C11
XDP_RSVD_00
XDP_RSVD_01
XDP_RSVD_02
XDP_RSVD_03
XDP_RSVD_04
XDP_RSVD_05
XDP_RSVD_06
XDP_RSVD_07
XDP_RSVD_08
XDP_RSVD_09
XDP_RSVD_10
XDP_RSVD_11
XDP_RSVD_12
XDP_RSVD_13
XDP_RSVD_14
XDP_RSVD_15
XDP_RSVD_16
XDP_RSVD_17
REV = 1.1
CRT_HSYNC
CRT_VSYNC
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_IRTN
M30
GMCH_CRT_HSYNC_R
M29
GMCH_CRT_VSYNC_R
N31
P30
P29
N30
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
2
470P_0402_50V7K
N475@
GMCH_CRT_R (10)
GMCH_CRT_G (10)
GMCH_CRT_B (10)
REV = 1.1
CRT_DDC_DATA
CRT_DDC_CLK
DAC_IREF
REFCLKINP
REFCLKINN
REFSSCLKINP
REFSSCLKINN
L31
L30
P28
Y30
Y29
AA30
AA31
GMCH_CRT_DATA (10)
GMCH_CRT_CLK (10)
R201
665_0402_1%
CPU_DREFCLK
CPU_DREFCLK#
CPU_SSCDREFCLK
CPU_SSCDREFCLK#
CPU_DREFCLK (8)
CPU_DREFCLK# (8)
CPU_SSCDREFCLK (8)
CPU_SSCDREFCLK# (8)
ICH
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
LVDS_ACLK#
LVDS_ACLK
LVDS_A0#
LVDS_A0
LVDS_A1#
LVDS_A1
LVDS_A2#
LVDS_A2
R151
2.37K_0402_1%
GMCH_ENBKL
0_0402_5%
R213
@
U25
U26
R23
R24
N26
N27
R26
R27
R22
J28
N22
N23
L27
L26
L23
K25
K23
K24
H26
LA_CLKN
LA_CLKP
LA_DATAN_0
LA_DATAP_0
LA_DATAN_1
LA_DATAP_1
LA_DATAN_2
LA_DATAP_2
LIBG
LVBG
LVREFH
LVREFL
LBKLT_EN
LBKLT_CTL
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
SMI#
A20M#
FERR#
LINT0
LINT1
IGNNE#
STPCLK#
DPRSTP#
DPSLP#
INIT#
PRDY#
PREQ#
E7
H7
H6
F10
F11
E5
F8
G6
G10
G8
E11
F15
E13
H_SMI#
H_A20M#
H_FERR#
H_INTR
H_NMI
H_IGNNE#
H_STPCLK#
H_DPRSTP#
H_DPSLP#
H_INIT#
XDP_PRDY#
XDP_PREQ#
H_THERMTRIP#
H_SMI# (12)
H_A20M# (12)
H_FERR# (12)
H_INTR (12)
H_NMI
(12)
H_IGNNE# (12)
H_STPCLK# (12)
H_DPRSTP# (13)
H_DPSLP# (13)
H_INIT# (12)
XDP_PRDY# (4)
XDP_PREQ# (4)
H_THERMTRIP# (12)
D
LVDS
(17) GMCH_ENBKL
(9,17) INVT_PW M
T37
L11
RSVD
0_0402_5%
R200
PM_EXTTS#0 (7)
PLTRST# (4,13,15,17,25,26,27)
THERMTRIP#
Add INVT_PWM
(9)
PM_DPRSLPVR (13)
PM_EXTTS#_1/DPRSLPVR
PM_EXTTS#_0
PWROK
RSTIN#
HPL_CLKINN
HPL_CLKINP
T18
T19
T20
T21
T22
T23
T24
T25
K29
J30
L5
AA3
W8
W9
PM_EXTTS#1
PM_EXTTS#0
H_PW ROK
PLTRST#
LVDS_SCL
(9)
LVDS_SDA
(9) GMCH_ENVDD
05/11
PROCHOT#
CPUPWRGOOD
C18
W1
H_PROCHOT#
H_PW RGD
H_PW RGD (4,13)
CLK_CPU_HPLCLK#
CLK_CPU_HPLCLK
C
CLK_CPU_HPLCLK# (8)
CLK_CPU_HPLCLK (8)
Del R323 05/11
GTLREF
VSS
A13
H27
H_GTLREF
C
AA7
AA6
R5
R6
AA21
W21
T21
V21
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
MISC
Modify 08/04
(4)
(4)
(4)
(4)
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
T48
T49
T50
T51
H_PW ROK
1
1
R305
@
2
VGATE
(8,13,17,36)
0_0402_5%
R306
2
0_0402_5%
G11
E15
G13
F13
B18
B20
C20
B21
RSVD
RSVD
BPM_1_0#
BPM_1_1#
BPM_1_2#
BPM_1_3#
BPM_2_0#/RSVD
BPM_2_1#/RSVD
BPM_2_2#/RSVD
BPM_2_3#/RSVD
BCLKN
BCLKP
BSEL_0
BSEL_1
BSEL_2
VID_0
VID_1
VID_2
VID_3
VID_4
VID_5
VID_6
RSVD
RSVD
RSVD
RSVD
RSVD_TP
RSVD_TP
EXTBGREF
L6
E17
H10
J10
K5
H5
K6
H30
H29
H28
G30
G29
F29
E29
L7
D20
H13
D18
K9
D19
K7
T26
T27
H_EXTBGREF
B
CLK_CPU_BCLK#
CLK_CPU_BCLK
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
CLK_CPU_BCLK# (8)
CLK_CPU_BCLK (8)
CPU_BSEL0 (8)
CPU_BSEL1 (8)
CPU_BSEL2 (8)
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
(36)
(36)
(36)
(36)
(36)
(36)
(36)
PCH_POK (13,17)
(4)
(4)
(4)
(4)
(4)
XDP_TDI
XDP_TDO
XDP_TCK
XDP_TMS
XDP_TRST#
T55
XDP_TDI
XDP_TDO
XDP_TCK
XDP_TMS
XDP_TRST#
H_THERMDA
H_THERMDC
G5
D14
D13
B14
C14
C16
D30
E30
RSVD
TDI
TDO
TCK
TMS
TRST#
THRMDA_1
THRMDC_1
B
Place closed to chipset
3 OF 6
PINEVIEW-M_FCBGA8559
T58
T59
T60
T61
T62
T63
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
PINEVIEW-M_FCBGA8559
GMCH_CRT_R
GMCH_CRT_G
GMCH_CRT_B
GMCH_ENBKL
1
2
150_0402_1%
R308
1
2
150_0402_1%
1
R309
2
150_0402_1%
R34
100K_0402_5%
R307
C30
D31
THRMDA_2/RSVD
THRMDC_2/RSVD
4 OF 6
H_PW RGD
+VCCP
+VCCP
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
+VCCP
+3VS
+3VS
R144
1K_0402_1%
H_EXTBGREF
H_GTLREF
1U_0603_10V6K
@
C939
R155
2K_0402_1%
@
C940
R143
10K_0402_5%
CPU
R244
976_0402_1%
1
1U_0603_10V6K
CPU THERMAL SENSOR
U2
EC_SMB_CK2
EC_SMB_DA2
1
R202
68_0402_5%
H_PROCHOT#
1
0.1U_0402_16V4Z
1
2
C80
PM_EXTTS#0
R156
3.3K_0402_1%
2
2
A
2
1
H_THERMDA
A
VDD
DP
DN
THERM#
SMCLK
SMDATA
ALERT#
GND
8
7
6
5
EC_SMB_CK2 (17,27)
EC_SMB_DA2 (17,27)
+3VS
C79
2
3
4
Close to Processor
pin
Security Classification
Issued Date
Close to Processor
pin
placed within 0.5"
of processor pin.
Title
placed within 0.5"
of processor pin.
1
H_THERMDC
2
2200P_0402_50V7K
2
R58
1
10K_0402_5%
Compal Secret Data
2006/08/18
Deciphered Date
Compal Electronics, Inc.
2007/8/18
EMC1402-1-ACZL-TR MSOP 8P SENSOR
Address:100_1100
5
4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Pineview(2/3)
Size
B
Date:
Document Number
LA-6421P
Thursday, June 03, 2010
Sheet
1
Rev
0.1
5
of
39

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