Acer Aspire 4251_4551_eMachines_D440_D640_D640G_Wistron_HM42-DN_JE40-DN_RevSA.pdf

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5
4
3
2
1
DDR3
D
800/1066/1333MHz
16,17
AMD Champlain CPU
S1G4 (45W)
638-Pin uFCPGA638
4,5,6,7
CRT
LCD
20
19
21
800/1066/1333 MHz
800/1066/1333MHz
16,17
OUT
DDR3
HDMI
HT 3.0
16X16
Madison
ATI
53,54,55,56,57
IN
CLK GEN.
3
ICS9LPRS480BKLFT 71.09480.A03
RTM880N-796-VB-GRT 71.00880.A03
C
North Bridge
AMD RS880M
CPU I/F
LVDS, CRT I/F
INTEGRATED GRAHPICS
16X
PCI EXPRESS GRAPHIC
LAN
Giga LAN
BCM57780
26
TXFM
27
INT MIC
30
8,9,10
Codec
ALC272
28
AZALIA
A-Link
4X1
PCIex1
Mini Card
WLAN
33
MIC In
30
South Bridge
AMD SB820
USB 2.0/1.1 ports
ETHERNET (10/100/1000Mb)
High Definition Audio
ATA 66/100
ACPI 1.1
LPC I/F
LPC BUS
BIOS
INT.SPKR
30
OP AMP
29
KBC
Novoton
NPCE781B
36
MXIC
MX25L1605
37
B
Line Out
30
PCI/PCI BRIDGE
11,12,13,14,15
Touch
Pad
38
CardReader
AU6433
32
INT.
KB
36
MS/MS Pro/xD
/MMC/SD
5 in 1
SATA
USB
32
HDD SATA
22
ODD SATA
A
Mini USB
Blue Tooth
24
USB
3 Port
Camera
25
Diserete Madison Hynix
A
23
Daughter Board
USB Board
Daughter Board
PWR+LED Board
5
4
3
版版
版版
版版
版版
2
HM42-DN Block Diagram
Project code: 91.4HD01.001
PCB P/N
: 48.4GX01.0SA
PCB
: 09919 SA
REVISION
:
PCB STACKUP
SYSTEM
TOP
VCC
S
S
GND
BOTTOM
DC/DC
46
OUTPUTS
5V_S5(5.5A)
3D3V_S5(5A)
D
RT8223
INPUTS
DCBATOUT
SYSTEM DC/DC
RT8209E
5V_S5
47
1D5V_S3(14A)
RT9026
5V_S5
47
0D75_S3(1.2A)
58, 59, 60, 61
DDR3
VRAM
RJ45
27
SYSTEM DC/DC
RT8209E
INPUTS
DCBATOUT
1D1V_S0(11A)
48
RT9025
3D3V_S5
48
1D1V_S5(1.4A)
C
RT9025
5V_S5
49
1D1V_VGA
RT9161
3D3V_S0
2D5V_S0
(200mA)
49
RT9025
1D5V_S3
49
1D05V_S0
(1.4A)
LPC
DEBUG
37
CONN.
CHARGER
BQ24745
INPUTS
50
OUTPUTS
CHG_PWR
DCBATOUT
18V
5V
6.0A
100mA
B
UP+5V
CPU DC/DC
ISL6265AHR
45
INPUTS OUTPUTS
VCC_CORE_S0
DCBATOUT
0~1.55V
18A
VDDNB
0~1.55V
4A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size
Document Number
Friday, March 26, 2010
Rev
A3
Date:
JE40-DN
-3
Sheet
1
1
of
63
5
4
3
2
1
D
D
C
C
B
B
A
Diserete Madison Hynix
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
History
Size
Document Number
Friday, March 26, 2010
Rev
A3
Date:
5
4
3
2
JE40-DN
-3
Sheet
1
2
of
63
5
4
3
2
1
3D3V_S0
1
R425
2
Do Not Stuff
3D3V_CLK_VDD
3D3V_S0
R177
1
1
1
1
1
1
1
1
SCD1U10V2KX-4GP
2R3J-GP
2
1
C358
Do Not Stuff
1
3D3V_48MPWR_S0
C359
SC1U10V2KX-1GP
1
C677
Do Not Stuff
1
C678
SC10U10V5ZY-1GP
DY
2
DY
C713
Do Not Stuff
Do Not Stuff
2
C689
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C680
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C360
Do Not Stuff
C724
SCD1U10V2KX-4GP
C707
SCD1U10V2KX-4GP
C727
DY
2
-1 0203
D
DY
2
3000mA.80ohm
2
Due to PLL issue on current clock chip, the SBlink clock
need to come from SRC clocks for RS740 and RS780.
Future clock chip revision will fix this.
2
2
2
2
2
2
D
3D3V_S0
1
R433
2
Do Not Stuff
1D1V_CLK_VDDIO
SC12P50V2JN-L1-GP
1
1
1
1
1
1
C733
1
U51
1D1V_CLK_VDDIO
26
25
48
47
16
17
11
3D3V_CLK_VDD
35
34
C
Clock chip has internal serial terminations
for differencial pairs, external resistors are
reserved for debug purpose.
1202
DY
2
82.30005.A51
X-14D31818M-50GP
1
C690
C691
SC10U6D3V3MX-GP
C702
SCD1U10V2KX-4GP
C712
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C681
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C682
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
2
X6
C734
C726
SCD1U10V2KX-4GP
3D3V_CLK_VDD
2ND = 82.30005.901
61
62
2
3
30
29
28
27
23
45
44
39
38
50
49
64
59
58
57
GEN_XTAL_IN
GEN_XTAL_OUT
Do Not Stuff
2
2
2
2
2
2
VDDATIG
VDDATIG_IO
VDDCPU
VDDCPU_IO
VDDSRC
VDDSRC_IO
VDDSRC_IO
VDDSB_SRC
VDDSB_SRC_IO
VDDSATA
VDD
VDDHTT
VDDREF
VDD48
PD#
X1
X2
SMBCLK
SMBDAT
ATIG0T_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS
CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#
CPUKG0T_LPRS
CPUKG0C_LPRS
2
1
2
SC12P50V2JN-L1-GP
CL=20pF±0.2pF
CLK_SMBCLK
R466
1
Not Stuff
2
Do
CLK_SMBDAT
R465
1
Not Stuff
2
Do
CLK_PCIE_PEG_1
R415
CLK_PCIE_PEG#_1
R416
CLK_NB_GFX_1
R417
1
CLK_NB_GFX#_1
R418
1
CLKREQ0#
CLKREQ2#
1
Do Not Stuff
2
Do
1
Not Stuff
2
Do Not Stuff
2
Do Not Stuff
2
SMBC0_SB 12,16,17
SMBD0_SB 12,16,17
-1 0203
CLK_PCIE_PEG
CLK_PCIE_PEG#
CLK_NB_GFX 9
CLK_NB_GFX# 9
53
53
1
R187
2
Do Not Stuff
C387
SC1U10V2KX-1GP
2
VDD_REF
3D3V_48MPWR_S0
PD#
40
4
55
56
63
51
22
21
20
19
15
14
13
12
9
8
42
41
6
5
37
36
32
31
54
53
TP101 Do Not Stuff
LAN_CLKREQ# 26
TP102 Do Not Stuff
WLAN_CLKREQ# 33
1
C
No mini2 card
CPU_CLK_1
CPU_CLK#_1
CLK_48
REF0
REF1
REF2
function
CLKREQ# Internal
pull Low
0908
CPU_CLK
CPU_CLK#
6
6
CLK48_USB
CLK48_6433
1
1
EC81
Do Not Stuff
12
32
SB A-Link
LAN
NB A-Link
MINI1
11 CLK_PCIE_SB
11 CLK_PCIE_SB#
26 CLK_PCIE_LAN
26 CLK_PCIE_LAN#
9 CLK_NB_GPPSB
9 CLK_NB_GPPSB#
33 CLK_PCIE_MINI1
33 CLK_PCIE_MINI1#
R419
1
Do Not Stuff
2
R420
1
Do Not Stuff
2
R421
1
Do Not Stuff
2
R422
1
Do Not Stuff
2
R435
1
Do Not Stuff
2
R438
1
Do Not Stuff
2
R442
1
Do Not Stuff
2
R448
1
Do Not Stuff
2
CLK_PCIE_SB_1
CLK_PCIE_SB#_1
CLK_PCIE_LAN_1
CLK_PCIE_LAN#_1
CLK_NB_GPPSB_1
CLK_NB_GPPSB#_1
CLK_PCIE_MINI1_1
CLK_PCIE_MINI1#_1
R475
1
Do Not Stuff
2
R474
1
Do Not Stuff
2
R471 10R2J-2-GP
1
2
1
2
R469
33R2J-2-GP
EC80
Do Not Stuff
0908
No mini2 card
function
function
No new card
54 OSC_SPREAD
54 CLK_27M_VGA
B
-2 0301
2
1116
9 CLK_NBHT_CLK
9 CLK_NBHT_CLK#
2
R451
1
Do Not Stuff
R455
1
Do Not Stuff
DY
CLK_SRC0T_LPRS
CLK_SRC0C_LPRS
0908
DY
R477
1
Do Not Stuff
2
R476
1
Do Not Stuff
2
CLK_NBHT_CLK_1
CLK_NBHT_CLK#_1
SRC0T_LPRS
SRC0C_LPRS
48MHZ_0
SRC1T_LPRS
SRC1C_LPRS
SRC2T_LPRS
REF0/SEL_HTT66
SRC2C_LPRS
REF1/SEL_SATA
SRC3T_LPRS
REF2/SEL_27
SRC3C_LPRS
SRC4T_LPRS
SRC4C_LPRS
SRC6T/SATAT_LPRS
GNDSATA
SRC6C/SATAC_LPRS
GNDATIG
SRC7T_LPRS/27MHZ_SS
GND
SRC7C_LPRS/27MHZ_NS
GNDHTT
GNDREF
GNDCPU
SB_SRC0T_LPRS
GND48
SB_SRC0C_LPRS
SB_SRC1T_LPRS
GNDSRC
SB_SRC1C_LPRS
GNDSRC
GNDSB_SRC
HTT0T_LPRS/66M
HTT0C_LPRS/66M
ICS9LPRS480BKLFT-GP
GND
DY
43
24
7
52
60
46
1
10
18
33
65
2
DY
2
B
R456
Do Not Stuff
NB CLOCK INPUT TABLE
1
DY
2
For SB820
R188
REF1
1
NB CLOCKS
HT_REFCLKP
RS880M
100M DIFF
NB HT
HT_REFCLKN
71.09480.A03
DY
CLK_SB_14M 12
100M DIFF
REFCLK_P
14M SE (1.1V)
REFCLK_N
vref
GFX_REFCLK
100M DIFF(IN/OUT)*
GPP_REFCLK
NC or 100M DIFF OUTPUT
2ND = 71.00880.A03
3D3V_S0
RN56
3D3V_S5
8
7
6
5
1
2
3
4
SRN10KJ-6-GP
WLAN_CLKREQ#
LAN_CLKREQ#
RUNPWROK_D
RUNPWROK_D
PD#
2
Do Not Stuff
R197
1008
2
1
DY
3D3V_S0
Do Not Stuff
42
1030
GPPSB_REFCLK
100M DIFF
DY
R193
Do Not Stuff
DY
R189
Do Not Stuff
* RS880M can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.
SEL_27
REF2
1*
0
REF0
REF1
REF2
SEL_SATA
REF1
SEL_HTT66
REF0
1
0*
1
0*
27MHz non-spreading singled clock on pin 5
and 27MHz spread clock on pin 6
100MHz differential spreading SRC clock
REF0
100MHz non-spreading differential SATA clock
2
100MHz differential spreading SRC clock
66MHz 3.3V single ended HTT clock
100MHz differential HTT clock
90D9R2F-1-GP
R185
1
R186
158R2F-GP
1
2
2
2
R190
10KR2J-3-GP
1
1
1
2
CLK_NB_14M 9
Diserete Madison Hynix
A
A
3
4
RN70
SRN10KJ-5-GP
DY
R478
Do Not Stuff
2
1
1
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU_CLK(200MHz)
-2 0301
OSC_14M_NB
RS880M 1.1V 158R/90.9R
CLKGEN_ICS9LPRS480
Size
Document Number
Rev
A3
Date:
5
4
3
2
JE40-DN
Friday, March 26, 2010
Sheet
1
-3
3
of
63
5
4
3
2
1
D
D
0904
1D1V_S0
1027 For AMD review request
SC10U6D3V3MX-GP
2
1
C279
SC10U6D3V3MX-GP
2
1
SC10U6D3V3MX-GP
2
1
C276
Place close to socket
C283
C281
SCD22U6D3V2KX-1GP
SCD22U6D3V2KX-1GP
1
1
1
C282
DY
Do Not Stuff
C272
DY
Do Not Stuff
C271
DY
Do Not Stuff
2
2
2
2
1
ACPU1A
D1
D2
D3
D4
E3
E2
E1
F1
G3
G2
G1
H1
J1
K1
L3
L2
L1
M1
N3
N2
E5
F5
F3
F4
G5
H5
H3
H4
K3
K4
L5
M5
M3
M4
N5
P5
J3
J2
J5
K5
N1
P1
P3
P4
VLDT_A0
VLDT_A1
VLDT_A2
VLDT_A3
1.5Amp
HT LINK
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
AE2
AE3
AE4
AE5
AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3
Y1
W1
Y4
Y3
R2
R3
T5
R5
HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7
HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15
HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
C
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15
HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1
HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H15
L0_CADIN_L15
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
C
B
B
HT_CPU_NB_CTL_H0 8
HT_CPU_NB_CTL_L0 8
HT_CPU_NB_CTL_H1 8
HT_CPU_NB_CTL_L1 8
SKT-CPU638P-GP-U2
SKT-BGA638H176
A
5
4
3
未未
未未
未未
未未
未未
未未
未未
未未
62.10055.111
2ND = 62.10055.181(ENG
)
Diserete Madison Hynix
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU_HT_LINK I/F_(1/4)
Size
Document Number
Rev
A3
Date:
2
JE40-DN
Friday, March 26, 2010
Sheet
1
-3
4
of
63
5
4
3
2
1
ACPU1C
MEM:DATA
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_DQS0_P
MEM_MA_DQS0_N
MEM_MA_DQS1_P
MEM_MA_DQS1_N
MEM_MA_DQS2_P
MEM_MA_DQS2_N
MEM_MA_DQS3_P
MEM_MA_DQS3_N
MEM_MA_DQS4_P
MEM_MA_DQS4_N
MEM_MA_DQS5_P
MEM_MA_DQS5_N
MEM_MA_DQS6_P
MEM_MA_DQS6_N
MEM_MA_DQS7_P
MEM_MA_DQS7_N
G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12
E12
C15
E19
F24
AC24
Y19
AB16
Y13
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
SKT-CPU638P-GP-U2
SKT-CPU638P-GP-U2
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
A12
B16
A22
E25
AB26
AE22
AC16
AD12
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
MEM_MB_DATA0 17
MEM_MB_DATA1 17
MEM_MB_DATA2 17
MEM_MB_DATA3 17
MEM_MB_DATA4 17
MEM_MB_DATA5 17
MEM_MB_DATA6 17
MEM_MB_DATA7 17
MEM_MB_DATA8 17
MEM_MB_DATA9 17
MEM_MB_DATA10 17
MEM_MB_DATA11 17
MEM_MB_DATA12 17
MEM_MB_DATA13 17
MEM_MB_DATA14 17
MEM_MB_DATA15 17
MEM_MB_DATA16 17
MEM_MB_DATA17 17
MEM_MB_DATA18 17
MEM_MB_DATA19 17
MEM_MB_DATA20 17
MEM_MB_DATA21 17
MEM_MB_DATA22 17
MEM_MB_DATA23 17
MEM_MB_DATA24 17
MEM_MB_DATA25 17
MEM_MB_DATA26 17
MEM_MB_DATA27 17
MEM_MB_DATA28 17
MEM_MB_DATA29 17
MEM_MB_DATA30 17
MEM_MB_DATA31 17
MEM_MB_DATA32 17
MEM_MB_DATA33 17
MEM_MB_DATA34 17
MEM_MB_DATA35 17
MEM_MB_DATA36 17
MEM_MB_DATA37 17
MEM_MB_DATA38 17
MEM_MB_DATA39 17
MEM_MB_DATA40 17
MEM_MB_DATA41 17
MEM_MB_DATA42 17
MEM_MB_DATA43 17
MEM_MB_DATA44 17
MEM_MB_DATA45 17
MEM_MB_DATA46 17
MEM_MB_DATA47 17
MEM_MB_DATA48 17
MEM_MB_DATA49 17
MEM_MB_DATA50 17
MEM_MB_DATA51 17
MEM_MB_DATA52 17
MEM_MB_DATA53 17
MEM_MB_DATA54 17
MEM_MB_DATA55 17
MEM_MB_DATA56 17
MEM_MB_DATA57 17
MEM_MB_DATA58 17
MEM_MB_DATA59 17
MEM_MB_DATA60 17
MEM_MB_DATA61 17
MEM_MB_DATA62 17
MEM_MB_DATA63 17
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
Place near to CPU
D
4.7u x 4
1
1
1
1
C310
Do Not Stuff
C312
Do Not Stuff
C311
SC4D7U6D3V3MX-2GP
SC4D7U6D3V3MX-2GP
C313
SC4D7U6D3V3MX-2GP
SC4D7U6D3V3MX-2GP
0.22u X 2
1
1
1
1
C305
Do Not Stuff
C302
Do Not Stuff
C303
SC180P50V2JN-1GP
C306
SC180P50V2JN-1GP
180P x 6
1
1
1
C300
Do Not Stuff
C307
DY
SC180P50V2JN-1GP
C308
SC180P50V2JN-1GP
C301
Do Not Stuff
Do Not Stuff
1
D
DY
2
DY
2
DY
2
DY
2
DY
2
2
2
2
2
2
2
0904
1D05V_S0
-1 0129
1500 mA
ACPU1B
2
CLOSE TO CPU
1D5V_S3
0904
MEMZP
MEMZN
M_A_RST#
AF10
AE10
H16
T19
V22
U21
V19
T20
U19
U20
V20
J22
J20
N19
N20
E16
F16
Y16
AA16
P19
P20
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
R20
R23
J21
R19
T22
T24
MEMZP
MEMZN
RSVD_M1
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MA_RAS_L
MA_CAS_L
MA_WE_L
VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CKE0
MB_CKE1
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_RAS_L
MB_CAS_L
MB_WE_L
Y10
VTT_SENSE
W17
B18
W26
W23
Y26
V26
W25
U22
J25
H26
P22
R22
A17
A18
AF18
AF17
R26
R25
P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24
R24
U26
J26
U25
U24
U23
M_B_RST#
1
0907
TP49 Do Not Stuff
VREF_DDR_CLAW
1
2
1
1
C328
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
C327
SCD1U10V2KX-4GP
2
C
1D5V_S3
R405
39D2R2F-L-GP
1
2
1
2
R409
39D2R2F-L-GP
16
M_A_RST#
0907
VDDR
C329
SCD1U10V2KX-4GP
1
0904
D10
C10
B10
AD10
VTT1
VTT2
VTT3
VTT4
MEM:CMD/CTRL/CLK
VTT5
VTT6
VTT7
VTT8
VTT9
W10
AC10
AB10
AA10
A10
C
RN26
4
3
16 MEM_MA0_ODT0
16 MEM_MA0_ODT1
M_B_RST#
17
SRN1KJ-7-GP
MEM_MB0_ODT0 17
MEM_MB0_ODT1 17
MEM_MB0_CS#0 17
MEM_MB0_CS#1 17
MEM_MB_CKE0 17
MEM_MB_CKE1 17
MEM_MB_CLK0_P 17
MEM_MB_CLK0_N 17
2
16 MEM_MA0_CS#0
16 MEM_MA0_CS#1
16 MEM_MA_CKE0
16 MEM_MA_CKE1
0922
2
16 MEM_MA_CLK0_P
16 MEM_MA_CLK0_N
0922
16 MEM_MA_CLK1_P
16 MEM_MA_CLK1_N
B
MEM_MB_CLK1_P 17
MEM_MB_CLK1_N 17
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
17
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
B
16 MEM_MA_BANK0
16 MEM_MA_BANK1
16 MEM_MA_BANK2
16 MEM_MA_RAS#
16 MEM_MA_CAS#
16 MEM_MA_WE#
MEM_MB_BANK0 17
MEM_MB_BANK1 17
MEM_MB_BANK2 17
MEM_MB_RAS# 17
MEM_MB_CAS# 17
MEM_MB_WE# 17
MEM_MB_DQS0_P
MEM_MB_DQS0_N
MEM_MB_DQS1_P
MEM_MB_DQS1_N
MEM_MB_DQS2_P
MEM_MB_DQS2_N
MEM_MB_DQS3_P
MEM_MB_DQS3_N
MEM_MB_DQS4_P
MEM_MB_DQS4_N
MEM_MB_DQS5_P
MEM_MB_DQS5_N
MEM_MB_DQS6_P
MEM_MB_DQS6_N
MEM_MB_DQS7_P
MEM_MB_DQS7_N
A
62.10055.111
62.10055.111
Diserete Madison Hynix
A
2ND = 62.10055.181
2ND = 62.10055.181
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU_DDR_(2/4)
Size
Document Number
Rev
A3
Date:
5
4
3
2
JE40-DN
Friday, March 26, 2010
Sheet
1
-3
5
of
63

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